468 lines
14 KiB
Verilog
468 lines
14 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
|
|
// Company:
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// File Name : QAM_TOP.v
|
|
// Department :
|
|
// Author : PWY
|
|
// Author's Tel :
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Relese History
|
|
// Version Date Author Description
|
|
// 0.4 2024-03-12 PWY
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Keywords :
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Parameter
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Purpose :
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Target Device:
|
|
// Tool versions:
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Reuse Issues
|
|
// Reset Strategy:
|
|
// Clock Domains:
|
|
// Critical Timing:
|
|
// Asynchronous I/F:
|
|
// Synthesizable (y/n):
|
|
// Other:
|
|
//-FHDR--------------------------------------------------------------------------------------------------------
|
|
`timescale 1ns/1ns
|
|
|
|
module QAM_TOP(
|
|
input clk
|
|
,input rstn
|
|
,input phase_manual_clr
|
|
,input phase_auto_clr
|
|
,input [47:0] fcw
|
|
,input [15:0] pha
|
|
|
|
,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix;
|
|
//2'b10:cos;2'b11:sin;
|
|
,input sel_sideband
|
|
|
|
,input din_vld
|
|
,input mix_enable
|
|
,output dout_vld
|
|
|
|
,input [15:0] din_i_0
|
|
,input [15:0] din_i_1
|
|
,input [15:0] din_i_2
|
|
,input [15:0] din_i_3
|
|
,input [15:0] din_i_4
|
|
,input [15:0] din_i_5
|
|
,input [15:0] din_i_6
|
|
,input [15:0] din_i_7
|
|
,input [15:0] din_i_8
|
|
,input [15:0] din_i_9
|
|
,input [15:0] din_i_10
|
|
,input [15:0] din_i_11
|
|
,input [15:0] din_i_12
|
|
,input [15:0] din_i_13
|
|
,input [15:0] din_i_14
|
|
,input [15:0] din_i_15
|
|
|
|
,input [15:0] din_q_0
|
|
,input [15:0] din_q_1
|
|
,input [15:0] din_q_2
|
|
,input [15:0] din_q_3
|
|
,input [15:0] din_q_4
|
|
,input [15:0] din_q_5
|
|
,input [15:0] din_q_6
|
|
,input [15:0] din_q_7
|
|
,input [15:0] din_q_8
|
|
,input [15:0] din_q_9
|
|
,input [15:0] din_q_10
|
|
,input [15:0] din_q_11
|
|
,input [15:0] din_q_12
|
|
,input [15:0] din_q_13
|
|
,input [15:0] din_q_14
|
|
,input [15:0] din_q_15
|
|
|
|
,output [15:0] dout_i_0
|
|
,output [15:0] dout_i_1
|
|
,output [15:0] dout_i_2
|
|
,output [15:0] dout_i_3
|
|
,output [15:0] dout_i_4
|
|
,output [15:0] dout_i_5
|
|
,output [15:0] dout_i_6
|
|
,output [15:0] dout_i_7
|
|
,output [15:0] dout_i_8
|
|
,output [15:0] dout_i_9
|
|
,output [15:0] dout_i_10
|
|
,output [15:0] dout_i_11
|
|
,output [15:0] dout_i_12
|
|
,output [15:0] dout_i_13
|
|
,output [15:0] dout_i_14
|
|
,output [15:0] dout_i_15
|
|
);
|
|
|
|
|
|
|
|
wire [15:0] cos_0;
|
|
wire [15:0] cos_1;
|
|
wire [15:0] cos_2;
|
|
wire [15:0] cos_3;
|
|
wire [15:0] cos_4;
|
|
wire [15:0] cos_5;
|
|
wire [15:0] cos_6;
|
|
wire [15:0] cos_7;
|
|
wire [15:0] cos_8;
|
|
wire [15:0] cos_9;
|
|
wire [15:0] cos_10;
|
|
wire [15:0] cos_11;
|
|
wire [15:0] cos_12;
|
|
wire [15:0] cos_13;
|
|
wire [15:0] cos_14;
|
|
wire [15:0] cos_15;
|
|
wire [15:0] sin_0;
|
|
wire [15:0] sin_1;
|
|
wire [15:0] sin_2;
|
|
wire [15:0] sin_3;
|
|
wire [15:0] sin_4;
|
|
wire [15:0] sin_5;
|
|
wire [15:0] sin_6;
|
|
wire [15:0] sin_7;
|
|
wire [15:0] sin_8;
|
|
wire [15:0] sin_9;
|
|
wire [15:0] sin_10;
|
|
wire [15:0] sin_11;
|
|
wire [15:0] sin_12;
|
|
wire [15:0] sin_13;
|
|
wire [15:0] sin_14;
|
|
wire [15:0] sin_15;
|
|
|
|
|
|
NCO inst_nco_0 (
|
|
.clk ( clk )
|
|
,.rstn ( rstn )
|
|
,.phase_manual_clr ( phase_manual_clr )
|
|
,.phase_auto_clr ( phase_auto_clr )
|
|
,.fcw ( fcw )
|
|
,.pha ( pha )
|
|
,.cos_0 ( cos_0 )
|
|
,.cos_1 ( cos_1 )
|
|
,.cos_2 ( cos_2 )
|
|
,.cos_3 ( cos_3 )
|
|
,.cos_4 ( cos_4 )
|
|
,.cos_5 ( cos_5 )
|
|
,.cos_6 ( cos_6 )
|
|
,.cos_7 ( cos_7 )
|
|
,.cos_8 ( cos_8 )
|
|
,.cos_9 ( cos_9 )
|
|
,.cos_10 ( cos_10 )
|
|
,.cos_11 ( cos_11 )
|
|
,.cos_12 ( cos_12 )
|
|
,.cos_13 ( cos_13 )
|
|
,.cos_14 ( cos_14 )
|
|
,.cos_15 ( cos_15 )
|
|
|
|
,.sin_0 ( sin_0 )
|
|
,.sin_1 ( sin_1 )
|
|
,.sin_2 ( sin_2 )
|
|
,.sin_3 ( sin_3 )
|
|
,.sin_4 ( sin_4 )
|
|
,.sin_5 ( sin_5 )
|
|
,.sin_6 ( sin_6 )
|
|
,.sin_7 ( sin_7 )
|
|
,.sin_8 ( sin_8 )
|
|
,.sin_9 ( sin_9 )
|
|
,.sin_10 ( sin_10 )
|
|
,.sin_11 ( sin_11 )
|
|
,.sin_12 ( sin_12 )
|
|
,.sin_13 ( sin_13 )
|
|
,.sin_14 ( sin_14 )
|
|
,.sin_15 ( sin_15 )
|
|
);
|
|
|
|
wire [15:0] dt_i_0;
|
|
wire [15:0] dt_i_1;
|
|
wire [15:0] dt_i_2;
|
|
wire [15:0] dt_i_3;
|
|
wire [15:0] dt_i_4;
|
|
wire [15:0] dt_i_5;
|
|
wire [15:0] dt_i_6;
|
|
wire [15:0] dt_i_7;
|
|
wire [15:0] dt_i_8;
|
|
wire [15:0] dt_i_9;
|
|
wire [15:0] dt_i_10;
|
|
wire [15:0] dt_i_11;
|
|
wire [15:0] dt_i_12;
|
|
wire [15:0] dt_i_13;
|
|
wire [15:0] dt_i_14;
|
|
wire [15:0] dt_i_15;
|
|
|
|
|
|
|
|
wire mix_dout_vld;
|
|
|
|
SSB inst_ssb_i (
|
|
.clk ( clk )
|
|
,.rstn ( rstn )
|
|
,.sel_sideband ( sel_sideband )
|
|
,.mix_enable ( mix_enable )
|
|
,.din_vld ( din_vld )
|
|
,.dout_vld ( mix_dout_vld )
|
|
|
|
,.din_i0 ( din_i_0 )
|
|
,.din_i1 ( din_i_1 )
|
|
,.din_i2 ( din_i_2 )
|
|
,.din_i3 ( din_i_3 )
|
|
,.din_i4 ( din_i_4 )
|
|
,.din_i5 ( din_i_5 )
|
|
,.din_i6 ( din_i_6 )
|
|
,.din_i7 ( din_i_7 )
|
|
,.din_i8 ( din_i_8 )
|
|
,.din_i9 ( din_i_9 )
|
|
,.din_i10 ( din_i_10 )
|
|
,.din_i11 ( din_i_11 )
|
|
,.din_i12 ( din_i_12 )
|
|
,.din_i13 ( din_i_13 )
|
|
,.din_i14 ( din_i_14 )
|
|
,.din_i15 ( din_i_15 )
|
|
|
|
,.din_q0 ( din_q_0 )
|
|
,.din_q1 ( din_q_1 )
|
|
,.din_q2 ( din_q_2 )
|
|
,.din_q3 ( din_q_3 )
|
|
,.din_q4 ( din_q_4 )
|
|
,.din_q5 ( din_q_5 )
|
|
,.din_q6 ( din_q_6 )
|
|
,.din_q7 ( din_q_7 )
|
|
,.din_q8 ( din_q_8 )
|
|
,.din_q9 ( din_q_9 )
|
|
,.din_q10 ( din_q_10 )
|
|
,.din_q11 ( din_q_11 )
|
|
,.din_q12 ( din_q_12 )
|
|
,.din_q13 ( din_q_13 )
|
|
,.din_q14 ( din_q_14 )
|
|
,.din_q15 ( din_q_15 )
|
|
|
|
,.cos_0 ( cos_0 )
|
|
,.cos_1 ( cos_1 )
|
|
,.cos_2 ( cos_2 )
|
|
,.cos_3 ( cos_3 )
|
|
,.cos_4 ( cos_4 )
|
|
,.cos_5 ( cos_5 )
|
|
,.cos_6 ( cos_6 )
|
|
,.cos_7 ( cos_7 )
|
|
,.cos_8 ( cos_8 )
|
|
,.cos_9 ( cos_9 )
|
|
,.cos_10 ( cos_10 )
|
|
,.cos_11 ( cos_11 )
|
|
,.cos_12 ( cos_12 )
|
|
,.cos_13 ( cos_13 )
|
|
,.cos_14 ( cos_14 )
|
|
,.cos_15 ( cos_15 )
|
|
|
|
,.sin_0 ( sin_0 )
|
|
,.sin_1 ( sin_1 )
|
|
,.sin_2 ( sin_2 )
|
|
,.sin_3 ( sin_3 )
|
|
,.sin_4 ( sin_4 )
|
|
,.sin_5 ( sin_5 )
|
|
,.sin_6 ( sin_6 )
|
|
,.sin_7 ( sin_7 )
|
|
,.sin_8 ( sin_8 )
|
|
,.sin_9 ( sin_9 )
|
|
,.sin_10 ( sin_10 )
|
|
,.sin_11 ( sin_11 )
|
|
,.sin_12 ( sin_12 )
|
|
,.sin_13 ( sin_13 )
|
|
,.sin_14 ( sin_14 )
|
|
,.sin_15 ( sin_15 )
|
|
|
|
,.dout_0 ( dt_i_0 )
|
|
,.dout_1 ( dt_i_1 )
|
|
,.dout_2 ( dt_i_2 )
|
|
,.dout_3 ( dt_i_3 )
|
|
,.dout_4 ( dt_i_4 )
|
|
,.dout_5 ( dt_i_5 )
|
|
,.dout_6 ( dt_i_6 )
|
|
,.dout_7 ( dt_i_7 )
|
|
,.dout_8 ( dt_i_8 )
|
|
,.dout_9 ( dt_i_9 )
|
|
,.dout_10 ( dt_i_10 )
|
|
,.dout_11 ( dt_i_11 )
|
|
,.dout_12 ( dt_i_12 )
|
|
,.dout_13 ( dt_i_13 )
|
|
,.dout_14 ( dt_i_14 )
|
|
,.dout_15 ( dt_i_15 )
|
|
|
|
);
|
|
|
|
|
|
reg [15:0] dout_i_r0;
|
|
reg [15:0] dout_i_r1;
|
|
reg [15:0] dout_i_r2;
|
|
reg [15:0] dout_i_r3;
|
|
reg [15:0] dout_i_r4;
|
|
reg [15:0] dout_i_r5;
|
|
reg [15:0] dout_i_r6;
|
|
reg [15:0] dout_i_r7;
|
|
reg [15:0] dout_i_r8;
|
|
reg [15:0] dout_i_r9;
|
|
reg [15:0] dout_i_r10;
|
|
reg [15:0] dout_i_r11;
|
|
reg [15:0] dout_i_r12;
|
|
reg [15:0] dout_i_r13;
|
|
reg [15:0] dout_i_r14;
|
|
reg [15:0] dout_i_r15;
|
|
|
|
wire dout_vld_w = (qam_mod == 2'b00) ? din_vld :
|
|
(qam_mod == 2'b01) ? mix_dout_vld :
|
|
1'b1 ;
|
|
|
|
|
|
always@(posedge clk or negedge rstn) begin
|
|
if(!rstn) begin
|
|
dout_i_r0 <= 16'h0;
|
|
dout_i_r1 <= 16'h0;
|
|
dout_i_r2 <= 16'h0;
|
|
dout_i_r3 <= 16'h0;
|
|
dout_i_r4 <= 16'h0;
|
|
dout_i_r5 <= 16'h0;
|
|
dout_i_r6 <= 16'h0;
|
|
dout_i_r7 <= 16'h0;
|
|
dout_i_r8 <= 16'h0;
|
|
dout_i_r9 <= 16'h0;
|
|
dout_i_r10 <= 16'h0;
|
|
dout_i_r11 <= 16'h0;
|
|
dout_i_r12 <= 16'h0;
|
|
dout_i_r13 <= 16'h0;
|
|
dout_i_r14 <= 16'h0;
|
|
dout_i_r15 <= 16'h0;
|
|
end
|
|
else if(dout_vld_w) begin
|
|
case(qam_mod)
|
|
2'b00 : begin
|
|
dout_i_r0 <= din_i_0;
|
|
dout_i_r1 <= din_i_1;
|
|
dout_i_r2 <= din_i_2;
|
|
dout_i_r3 <= din_i_3;
|
|
dout_i_r4 <= din_i_4;
|
|
dout_i_r5 <= din_i_5;
|
|
dout_i_r6 <= din_i_6;
|
|
dout_i_r7 <= din_i_7;
|
|
dout_i_r8 <= din_i_8;
|
|
dout_i_r9 <= din_i_9;
|
|
dout_i_r10 <= din_i_10;
|
|
dout_i_r11 <= din_i_11;
|
|
dout_i_r12 <= din_i_12;
|
|
dout_i_r13 <= din_i_13;
|
|
dout_i_r14 <= din_i_14;
|
|
dout_i_r15 <= din_i_15;
|
|
end
|
|
2'b01 : begin
|
|
dout_i_r0 <= dt_i_0;
|
|
dout_i_r1 <= dt_i_1;
|
|
dout_i_r2 <= dt_i_2;
|
|
dout_i_r3 <= dt_i_3;
|
|
dout_i_r4 <= dt_i_4;
|
|
dout_i_r5 <= dt_i_5;
|
|
dout_i_r6 <= dt_i_6;
|
|
dout_i_r7 <= dt_i_7;
|
|
dout_i_r8 <= dt_i_8;
|
|
dout_i_r9 <= dt_i_9;
|
|
dout_i_r10 <= dt_i_10;
|
|
dout_i_r11 <= dt_i_11;
|
|
dout_i_r12 <= dt_i_12;
|
|
dout_i_r13 <= dt_i_13;
|
|
dout_i_r14 <= dt_i_14;
|
|
dout_i_r15 <= dt_i_15;
|
|
end
|
|
2'b10 : begin
|
|
dout_i_r0 <= cos_0;
|
|
dout_i_r1 <= cos_1;
|
|
dout_i_r2 <= cos_2;
|
|
dout_i_r3 <= cos_3;
|
|
dout_i_r4 <= cos_4;
|
|
dout_i_r5 <= cos_5;
|
|
dout_i_r6 <= cos_6;
|
|
dout_i_r7 <= cos_7;
|
|
dout_i_r8 <= cos_8;
|
|
dout_i_r9 <= cos_9;
|
|
dout_i_r10 <= cos_10;
|
|
dout_i_r11 <= cos_11;
|
|
dout_i_r12 <= cos_12;
|
|
dout_i_r13 <= cos_13;
|
|
dout_i_r14 <= cos_14;
|
|
dout_i_r15 <= cos_15;
|
|
end
|
|
default : begin
|
|
dout_i_r0 <= din_q_0 ;
|
|
dout_i_r1 <= din_q_1 ;
|
|
dout_i_r2 <= din_q_2 ;
|
|
dout_i_r3 <= din_q_3 ;
|
|
dout_i_r4 <= din_q_4 ;
|
|
dout_i_r5 <= din_q_5 ;
|
|
dout_i_r6 <= din_q_6 ;
|
|
dout_i_r7 <= din_q_7 ;
|
|
dout_i_r8 <= din_q_8 ;
|
|
dout_i_r9 <= din_q_9 ;
|
|
dout_i_r10 <= din_q_10 ;
|
|
dout_i_r11 <= din_q_11 ;
|
|
dout_i_r12 <= din_q_12 ;
|
|
dout_i_r13 <= din_q_13 ;
|
|
dout_i_r14 <= din_q_14 ;
|
|
dout_i_r15 <= din_q_15 ;
|
|
end
|
|
endcase
|
|
end
|
|
else begin
|
|
dout_i_r0 <= 16'h0;
|
|
dout_i_r1 <= 16'h0;
|
|
dout_i_r2 <= 16'h0;
|
|
dout_i_r3 <= 16'h0;
|
|
dout_i_r4 <= 16'h0;
|
|
dout_i_r5 <= 16'h0;
|
|
dout_i_r6 <= 16'h0;
|
|
dout_i_r7 <= 16'h0;
|
|
dout_i_r8 <= 16'h0;
|
|
dout_i_r9 <= 16'h0;
|
|
dout_i_r10 <= 16'h0;
|
|
dout_i_r11 <= 16'h0;
|
|
dout_i_r12 <= 16'h0;
|
|
dout_i_r13 <= 16'h0;
|
|
dout_i_r14 <= 16'h0;
|
|
dout_i_r15 <= 16'h0;
|
|
end
|
|
end
|
|
|
|
|
|
assign dout_i_0 = dout_i_r0 ;
|
|
assign dout_i_1 = dout_i_r1 ;
|
|
assign dout_i_2 = dout_i_r2 ;
|
|
assign dout_i_3 = dout_i_r3 ;
|
|
assign dout_i_4 = dout_i_r4 ;
|
|
assign dout_i_5 = dout_i_r5 ;
|
|
assign dout_i_6 = dout_i_r6 ;
|
|
assign dout_i_7 = dout_i_r7 ;
|
|
assign dout_i_8 = dout_i_r8 ;
|
|
assign dout_i_9 = dout_i_r9 ;
|
|
assign dout_i_10 = dout_i_r10 ;
|
|
assign dout_i_11 = dout_i_r11 ;
|
|
assign dout_i_12 = dout_i_r12 ;
|
|
assign dout_i_13 = dout_i_r13 ;
|
|
assign dout_i_14 = dout_i_r14 ;
|
|
assign dout_i_15 = dout_i_r15 ;
|
|
|
|
|
|
reg dout_vld_r;
|
|
|
|
always @(posedge clk or negedge rstn) begin
|
|
if(rstn == 1'b0) begin
|
|
dout_vld_r <= 1'b0;
|
|
end
|
|
else begin
|
|
dout_vld_r <= dout_vld_w;
|
|
end
|
|
end
|
|
|
|
assign dout_vld = dout_vld_r;
|
|
|
|
endmodule
|