320 lines
6.3 KiB
Verilog
320 lines
6.3 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : duc_hb4_top_s3.v
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// Department :
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// Author :
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.8 2024-03-26 thfu modify delay
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module DUC_HB4_TOP_S3 (clkl,
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rstn,
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din0,
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din1,
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din2,
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din3,
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din4,
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din5,
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din6,
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din7,
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dout_p0,
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dout_p1,
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dout_p2,
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dout_p3,
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dout_p4,
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dout_p5,
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dout_p6,
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dout_p7,
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dout_p8,
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dout_p9,
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dout_pa,
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dout_pb,
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dout_pc,
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dout_pd,
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dout_pe,
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dout_pf
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);
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input clkl,rstn;
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input [15:0] din0;
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input [15:0] din1;
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input [15:0] din2;
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input [15:0] din3;
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input [15:0] din4;
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input [15:0] din5;
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input [15:0] din6;
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input [15:0] din7;
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output [15:0] dout_p0;
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output [15:0] dout_p1;
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output [15:0] dout_p2;
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output [15:0] dout_p3;
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output [15:0] dout_p4;
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output [15:0] dout_p5;
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output [15:0] dout_p6;
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output [15:0] dout_p7;
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output [15:0] dout_p8;
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output [15:0] dout_p9;
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output [15:0] dout_pa;
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output [15:0] dout_pb;
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output [15:0] dout_pc;
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output [15:0] dout_pd;
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output [15:0] dout_pe;
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output [15:0] dout_pf;
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reg [15:0] din_r1;
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reg [15:0] din_r2;
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reg [15:0] din_r3;
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reg [15:0] din_r4;
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reg [15:0] din_r5;
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reg [15:0] din_r6;
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reg [15:0] din_r7;
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reg [15:0] din_r8;
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reg [15:0] din_r9;
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reg [15:0] din_r10;
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reg [15:0] din_r11;
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reg [15:0] din_r12;
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reg [15:0] din_r13;
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reg [15:0] din_r14;
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reg [15:0] din_r15;
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reg [15:0] din_r16;
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reg [15:0] din_r17;
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reg [15:0] din_r18;
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reg [15:0] din_r19;
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reg [15:0] din_r20;
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reg [15:0] din_r21;
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reg [15:0] din_r22;
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reg [15:0] din_r23;
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reg [15:0] din_r24;
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reg [15:0] din_r25;
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reg [15:0] din_r26;
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reg [15:0] din_r27;
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reg [15:0] din_r28;
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reg [15:0] din_r29;
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reg [15:0] din_r30;
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reg [15:0] din_r31;
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reg [15:0] din_r32;
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reg [15:0] din_r33;
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reg [15:0] din_r34;
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reg [15:0] din_r35;
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always@(posedge clkl or negedge rstn)
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if(!rstn)
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begin
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din_r1 <= 'b0;
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din_r2 <= 'b0;
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din_r3 <= 'b0;
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din_r4 <= 'b0;
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din_r5 <= 'b0;
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din_r6 <= 'b0;
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din_r7 <= 'b0;
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din_r8 <= 'b0;
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din_r9 <= 'b0;
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din_r10 <= 'b0;
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din_r11 <= 'b0;
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din_r12 <= 'b0;
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din_r13 <= 'b0;
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din_r14 <= 'b0;
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end
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else
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begin
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din_r1 <= din7;
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din_r2 <= din6;
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din_r3 <= din5;
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din_r4 <= din4;
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din_r5 <= din3;
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din_r6 <= din2;
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din_r7 <= din1;
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din_r8 <= din0;
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din_r9 <= din_r1;
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din_r17 <= din_r9;
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din_r25 <= din_r17;
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din_r33 <= din_r25;
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din_r10 <= din_r2;
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din_r18 <= din_r10;
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din_r26 <= din_r18;
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din_r34 <= din_r26;
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din_r11 <= din_r3;
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din_r19 <= din_r11;
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din_r27 <= din_r19;
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din_r35 <= din_r27;
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din_r12 <= din_r4;
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din_r20 <= din_r12;
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din_r28 <= din_r20;
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din_r13 <= din_r5;
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din_r21 <= din_r13;
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din_r29 <= din_r21;
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din_r14 <= din_r6;
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din_r22 <= din_r14;
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din_r30 <= din_r22;
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din_r15 <= din_r7;
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din_r23 <= din_r15;
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din_r31 <= din_r23;
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din_r16 <= din_r8;
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din_r24 <= din_r16;
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din_r32 <= din_r24;
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end
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DUC_HB4 inst0_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din7),
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.din_1 (din6),
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.din_2 (din5),
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.din_3 (din4), //dout_p0
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.din_4 (din3),
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.din_5 (din2),
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.dout (dout_p1)
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);
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assign dout_p0 = din_r28;
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DUC_HB4 inst1_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din6),
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.din_1 (din5),
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.din_2 (din4),
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.din_3 (din3), //dout_p2
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.din_4 (din2),
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.din_5 (din1),
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.dout (dout_p3)
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);
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assign dout_p2 = din_r29;
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DUC_HB4 inst2_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din5),
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.din_1 (din4),
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.din_2 (din3),
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.din_3 (din2), //dout_p4
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.din_4 (din1),
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.din_5 (din0),
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.dout (dout_p5)
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);
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assign dout_p4 = din_r30;
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DUC_HB4 inst3_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din4),
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.din_1 (din3),
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.din_2 (din2),
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.din_3 (din1), //dout_p6
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.din_4 (din0),
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.din_5 (din_r1),
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.dout (dout_p7)
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);
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assign dout_p6 = din_r31;
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DUC_HB4 inst4_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din3),
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.din_1 (din2),
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.din_2 (din1),
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.din_3 (din0), //dout_p6
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.din_4 (din_r1),
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.din_5 (din_r2),
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.dout (dout_p9)
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);
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assign dout_p8 = din_r32;
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DUC_HB4 inst5_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din2),
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.din_1 (din1),
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.din_2 (din0),
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.din_3 (din_r1), //dout_p6
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.din_4 (din_r2),
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.din_5 (din_r3),
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.dout (dout_pb)
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);
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assign dout_pa = din_r33;
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DUC_HB4 inst6_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din1),
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.din_1 (din0),
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.din_2 (din_r1),
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.din_3 (din_r2), //dout_p6
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.din_4 (din_r3),
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.din_5 (din_r4),
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.dout (dout_pd)
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);
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assign dout_pc = din_r34;
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DUC_HB4 inst7_duc_hb4(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din0),
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.din_1 (din_r1),
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.din_2 (din_r2),
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.din_3 (din_r3), //dout_p6
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.din_4 (din_r4),
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.din_5 (din_r5),
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.dout (dout_pf)
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);
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assign dout_pe = din_r35;
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endmodule
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