170 lines
5.1 KiB
Verilog
170 lines
5.1 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : duc_hb4_shift.v
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// Department :
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// Author :
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.8 2024-03-26 thfu output register
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module DUC_HB4 (
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clk,
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rstn,
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din_0,
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din_1,
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din_2,
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din_3,
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din_4,
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din_5,
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dout
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);
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input clk;
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input rstn;
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input signed [15:0] din_0;
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input signed [15:0] din_1;
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input signed [15:0] din_2;
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input signed [15:0] din_3;
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input signed [15:0] din_4;
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input signed [15:0] din_5;
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output signed [15:0] dout;
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wire signed [15:0] din_0;
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wire signed [15:0] din_2;
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wire signed [15:0] din_4;
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wire signed [15:0] din_5;
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wire signed [15:0] din_6;
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parameter c0 = 14'd101;
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parameter c1 = -14'd814;
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parameter c2 = 14'd4809;
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reg signed [16:0] sum_0_5;
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reg signed [16:0] sum_1_4;
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reg signed [16:0] sum_2_3;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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sum_0_5 <= 'h0;
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sum_1_4 <= 'h0;
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sum_2_3 <= 'h0;
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end
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else
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begin
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sum_0_5 <= {din_0[15],din_0} + {din_5[15],din_5};
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sum_1_4 <= {din_1[15],din_1} + {din_4[15],din_4};
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sum_2_3 <= {din_2[15],din_2} + {din_3[15],din_3};
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end
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wire signed [18:0] mult_c0_sum0;
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wire signed [20:0] mult_c0_sum1;
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wire signed [23:0] mult_c0_sum2;
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wire signed [24:0] mult_c0_sum3;
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assign mult_c0_sum0 = {sum_0_5,2'b0};
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assign mult_c0_sum1 = {sum_0_5,4'b0};
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assign mult_c0_sum2 = {sum_0_5,7'b0};
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assign mult_c0_sum3 = {sum_0_5,8'b0};
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reg signed [25:0] mult_c0_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c0_sum <= 'h0;
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else
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mult_c0_sum <= {{7{mult_c0_sum0[18]}},mult_c0_sum0} + {{5{mult_c0_sum1[20]}},mult_c0_sum1} + {{2{mult_c0_sum2[23]}},mult_c0_sum2} + {{1{mult_c0_sum3[24]}},mult_c0_sum3};
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wire signed [19:0] mult_c1_sum0;
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wire signed [22:0] mult_c1_sum1;
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wire signed [23:0] mult_c1_sum2;
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wire signed [26:0] mult_c1_sum3;
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wire signed [27:0] mult_c1_sum4;
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assign mult_c1_sum0 = {sum_1_4,3'b0};
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assign mult_c1_sum1 = {sum_1_4,6'b0};
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assign mult_c1_sum2 = {sum_1_4,7'b0};
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assign mult_c1_sum3 = {sum_1_4,10'b0};
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assign mult_c1_sum4 = {sum_1_4,11'b0};
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reg signed [28:0] mult_c1_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c1_sum <= 'h0;
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else
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mult_c1_sum <= -{{9{mult_c1_sum0[19]}},mult_c1_sum0} + {{6{mult_c1_sum1[22]}},mult_c1_sum1} + {{5{mult_c1_sum2[23]}},mult_c1_sum2} + {{2{mult_c1_sum3[26]}},mult_c1_sum3} + {{1{mult_c1_sum4[27]}},mult_c1_sum4};
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wire signed [18:0] mult_c2_sum0;
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wire signed [21:0] mult_c2_sum1;
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wire signed [24:0] mult_c2_sum2;
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wire signed [25:0] mult_c2_sum3;
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wire signed [27:0] mult_c2_sum4;
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wire signed [30:0] mult_c2_sum5;
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assign mult_c2_sum0 = {sum_2_3,2'b0};
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assign mult_c2_sum1 = {sum_2_3,5'b0};
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assign mult_c2_sum2 = {sum_2_3,8'b0};
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assign mult_c2_sum3 = {sum_2_3,9'b0};
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assign mult_c2_sum4 = {sum_2_3,11'b0};
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assign mult_c2_sum5 = {sum_2_3,14'b0};
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reg signed [31:0] mult_c2_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c2_sum <= 'h0;
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else
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mult_c2_sum <= {{13{mult_c2_sum0[18]}},mult_c2_sum0} + {{10{mult_c2_sum1[21]}},mult_c2_sum1} + {{7{mult_c2_sum2[24]}},mult_c2_sum2} + {{6{mult_c2_sum3[25]}},mult_c2_sum3} + {{4{mult_c2_sum4[27]}},mult_c2_sum4} + {{1{mult_c2_sum5[30]}},mult_c2_sum5};
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reg signed [32:0] mult_sum;
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wire signed [17:0] dout0_w;
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reg signed [15:0] dout0;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_sum <= 'h0;
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else
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mult_sum <= {{7{mult_c0_sum[25]}},mult_c0_sum} - {{4{mult_c1_sum[28]}},mult_c1_sum} + {{1{mult_c2_sum[31]}},mult_c2_sum};
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assign dout0_w = mult_sum[32:15]+mult_sum[14];
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always@(posedge clk or negedge rstn)
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if(!rstn)
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dout0 <= 'h0;
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else if(dout0_w[16:15]==2'b01)
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dout0 <= 16'd32767;
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else if(dout0_w[16:15]==2'b10)
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dout0 <= -16'd32768;
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else
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dout0 <= dout0_w[15:0];
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assign dout = dout0;
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endmodule
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