119 lines
2.1 KiB
Verilog
119 lines
2.1 KiB
Verilog
module DUC_HB2_TOP_S (clkl,
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rstn,
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din0,
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din1,
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dout_p0,
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dout_p1,
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dout_p2,
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dout_p3
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);
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input clkl,rstn;
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input [15:0] din0;
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input [15:0] din1;
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output [15:0] dout_p0;
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output [15:0] dout_p1;
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output [15:0] dout_p2;
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output [15:0] dout_p3;
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reg [15:0] din_r1;
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reg [15:0] din_r2;
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reg [15:0] din_r3;
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reg [15:0] din_r4;
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reg [15:0] din_r5;
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reg [15:0] din_r6;
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reg [15:0] din_r7;
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reg [15:0] din_r8;
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reg [15:0] din_r9;
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reg [15:0] din_r10;
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reg [15:0] din_r11;
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reg [15:0] din_r12;
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reg [15:0] din_r13;
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reg [15:0] din_r14;
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always@(posedge clkl or negedge rstn)
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if(!rstn)
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begin
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din_r1 <= 'b0;
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din_r2 <= 'b0;
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din_r3 <= 'b0;
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din_r4 <= 'b0;
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din_r5 <= 'b0;
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din_r6 <= 'b0;
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din_r7 <= 'b0;
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din_r8 <= 'b0;
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din_r9 <= 'b0;
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din_r10 <= 'b0;
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din_r11 <= 'b0;
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din_r12 <= 'b0;
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end
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else
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begin
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din_r1 <= din1;
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din_r3 <= din_r1;
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din_r5 <= din_r3;
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din_r7 <= din_r5;
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din_r9 <= din_r7;
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din_r11 <= din_r9;
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din_r13 <= din_r11;
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din_r2 <= din0;
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din_r4 <= din_r2;
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din_r6 <= din_r4;
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din_r8 <= din_r6;
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din_r10 <= din_r8;
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din_r12 <= din_r10;
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din_r14 <= din_r12;
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end
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DUC_HB2 inst0_duc_hb2(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din1),
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.din_1 (din0),
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.din_2 (din_r1),
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.din_3 (din_r2),
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.din_4 (din_r3),
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.din_5 (din_r4),
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.din_6 (din_r5), //dout_p0
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.din_7 (din_r6),
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.din_8 (din_r7),
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.din_9 (din_r8),
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.din_a (din_r9),
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.din_b (din_r10),
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.dout (dout_p1)
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);
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assign dout_p0 = din_r13;
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DUC_HB2 inst1_duc_hb2(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din0),
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.din_1 (din_r1),
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.din_2 (din_r2),
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.din_3 (din_r3),
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.din_4 (din_r4),
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.din_5 (din_r5),
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.din_6 (din_r6), //dout_p2
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.din_7 (din_r7),
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.din_8 (din_r8),
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.din_9 (din_r9),
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.din_a (din_r10),
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.din_b (din_r11),
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.dout (dout_p3)
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);
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assign dout_p2 = din_r14;
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endmodule
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