260 lines
9.9 KiB
Verilog
260 lines
9.9 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : duc_hb2_shift.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.8 2024-03-26 thfu add pipeline
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module DUC_HB2 (
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clk,
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rstn,
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din_0,
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din_1,
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din_2,
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din_3,
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din_4,
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din_5,
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din_6,
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din_7,
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din_8,
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din_9,
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din_a,
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din_b,
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dout
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);
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input clk;
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input rstn;
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input signed [15:0] din_0;
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input signed [15:0] din_1;
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input signed [15:0] din_2;
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input signed [15:0] din_3;
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input signed [15:0] din_4;
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input signed [15:0] din_5;
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input signed [15:0] din_6;
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input signed [15:0] din_7;
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input signed [15:0] din_8;
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input signed [15:0] din_9;
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input signed [15:0] din_a;
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input signed [15:0] din_b;
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output signed [15:0] dout;
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parameter c0 = -18'd91;
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parameter c1 = 18'd659;
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parameter c2 = -18'd2663;
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parameter c3 = 18'd8009;
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parameter c4 = -18'd21490;
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parameter c5 = 18'd81112;
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reg signed [16:0] sum_0_b;
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reg signed [16:0] sum_1_a;
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reg signed [16:0] sum_2_9;
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reg signed [16:0] sum_3_8;
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reg signed [16:0] sum_4_7;
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reg signed [16:0] sum_5_6;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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sum_0_b <= 'h0;
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sum_1_a <= 'h0;
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sum_2_9 <= 'h0;
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sum_3_8 <= 'h0;
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sum_4_7 <= 'h0;
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sum_5_6 <= 'h0;
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end
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else
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begin
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sum_0_b <= {{1 {din_0[15]}},din_0} + {{1 {din_b[15]}},din_b};
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sum_1_a <= {{1 {din_1[15]}},din_1} + {{1 {din_a[15]}},din_a};
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sum_2_9 <= {{1 {din_2[15]}},din_2} + {{1 {din_9[15]}},din_9};
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sum_3_8 <= {{1 {din_3[15]}},din_3} + {{1 {din_8[15]}},din_8};
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sum_4_7 <= {{1 {din_4[15]}},din_4} + {{1 {din_7[15]}},din_7};
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sum_5_6 <= {{1 {din_5[15]}},din_5} + {{1 {din_6[15]}},din_6};
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end
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wire signed [16:0] mult_c0_sum0;
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wire signed [19:0] mult_c0_sum1;
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wire signed [21:0] mult_c0_sum2;
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assign mult_c0_sum0 = sum_0_b;
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assign mult_c0_sum1 = {sum_0_b,3'b0};
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assign mult_c0_sum2 = {sum_0_b,5'b0};
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reg signed [22:0] mult_c0_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c0_sum <= 'h0;
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else
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mult_c0_sum <= -{{6{mult_c0_sum0[16]}},mult_c0_sum0} - {{3{mult_c0_sum1[19]}},mult_c0_sum1} + {{1{mult_c0_sum2[21]}},mult_c0_sum2};
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wire signed [16:0] mult_c1_sum0;
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wire signed [18:0] mult_c1_sum1;
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wire signed [21:0] mult_c1_sum2;
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wire signed [23:0] mult_c1_sum3;
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assign mult_c1_sum0 = sum_1_a;
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assign mult_c1_sum1 = {sum_1_a,2'b0};
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assign mult_c1_sum2 = {sum_1_a,5'b0};
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assign mult_c1_sum3 = {sum_1_a,7'b0};
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reg signed [24:0] mult_c1_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c1_sum <= 'h0;
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else
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mult_c1_sum <= {{8{mult_c1_sum0[16]}},mult_c1_sum0} + {{6{mult_c1_sum1[18]}},mult_c1_sum1} + {{3{mult_c1_sum2[21]}},mult_c1_sum2} + {{1{mult_c1_sum3[23]}},mult_c1_sum3};
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wire signed [17:0] mult_c2_sum0;
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wire signed [18:0] mult_c2_sum1;
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wire signed [21:0] mult_c2_sum2;
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wire signed [22:0] mult_c2_sum3;
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wire signed [24:0] mult_c2_sum4;
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wire signed [26:0] mult_c2_sum5;
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assign mult_c2_sum0 = {sum_2_9,1'b0};
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assign mult_c2_sum1 = {sum_2_9,2'b0};
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assign mult_c2_sum2 = {sum_2_9,5'b0};
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assign mult_c2_sum3 = {sum_2_9,6'b0};
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assign mult_c2_sum4 = {sum_2_9,8'b0};
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assign mult_c2_sum5 = {sum_2_9,10'b0};
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reg signed [27:0] mult_c2_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c2_sum <= 'h0;
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else
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mult_c2_sum <= -{{10{mult_c2_sum0[17]}},mult_c2_sum0} - {{9{mult_c2_sum1[18]}},mult_c2_sum1} - {{6{mult_c2_sum2[21]}},mult_c2_sum2} - {{5{mult_c2_sum3[22]}},mult_c2_sum3} - {{3{mult_c2_sum4[24]}},mult_c2_sum4} + {{1{mult_c2_sum5[26]}},mult_c2_sum5};
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wire signed [17:0] mult_c3_sum0;
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wire signed [20:0] mult_c3_sum1;
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wire signed [22:0] mult_c3_sum2;
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wire signed [27:0] mult_c3_sum3;
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assign mult_c3_sum0 = {sum_3_8,1'b0};
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assign mult_c3_sum1 = {sum_3_8,4'b0};
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assign mult_c3_sum2 = {sum_3_8,6'b0};
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assign mult_c3_sum3 = {sum_3_8,11'b0};
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reg signed [28:0] mult_c3_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c3_sum <= 'h0;
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else
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mult_c3_sum <= {{11{mult_c3_sum0[17]}},mult_c3_sum0} + {{8{mult_c3_sum1[20]}},mult_c3_sum1} - {{6{mult_c3_sum2[22]}},mult_c3_sum2} + {{1{mult_c3_sum3[27]}},mult_c3_sum3};
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wire signed [16:0] mult_c4_sum0;
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wire signed [18:0] mult_c4_sum1;
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wire signed [24:0] mult_c4_sum2;
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wire signed [26:0] mult_c4_sum3;
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wire signed [28:0] mult_c4_sum4;
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assign mult_c4_sum0 = sum_4_7;
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assign mult_c4_sum1 = {sum_4_7,2'b0};
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assign mult_c4_sum2 = {sum_4_7,8'b0};
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assign mult_c4_sum3 = {sum_4_7,10'b0};
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assign mult_c4_sum4 = {sum_4_7,12'b0};
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reg signed [29:0] mult_c4_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c4_sum <= 'h0;
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else
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mult_c4_sum <= {{13{mult_c4_sum0[16]}},mult_c4_sum0} - {{11{mult_c4_sum1[18]}},mult_c4_sum1} + {{5{mult_c4_sum2[24]}},mult_c4_sum2} + {{3{mult_c4_sum3[26]}},mult_c4_sum3} + {{1{mult_c4_sum4[28]}},mult_c4_sum4};
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wire signed [17:0] mult_c5_sum0;
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wire signed [18:0] mult_c5_sum1;
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wire signed [20:0] mult_c5_sum2;
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wire signed [21:0] mult_c5_sum3;
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wire signed [24:0] mult_c5_sum4;
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wire signed [28:0] mult_c5_sum5;
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wire signed [30:0] mult_c5_sum6;
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assign mult_c5_sum0 = {sum_5_6,1'b0};
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assign mult_c5_sum1 = {sum_5_6,2'b0};
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assign mult_c5_sum2 = {sum_5_6,4'b0};
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assign mult_c5_sum3 = {sum_5_6,5'b0};
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assign mult_c5_sum4 = {sum_5_6,8'b0};
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assign mult_c5_sum5 = {sum_5_6,12'b0};
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assign mult_c5_sum6 = {sum_5_6,14'b0};
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reg signed [31:0] mult_c5_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c5_sum <= 'h0;
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else
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mult_c5_sum <= {{14{mult_c5_sum0[17]}},mult_c5_sum0} + {{13{mult_c5_sum1[18]}},mult_c5_sum1} + {{11{mult_c5_sum2[20]}},mult_c5_sum2} + {{10{mult_c5_sum3[21]}},mult_c5_sum3} - {{7{mult_c5_sum4[24]}},mult_c5_sum4} + {{3{mult_c5_sum5[28]}},mult_c5_sum5} + {{1{mult_c5_sum6[30]}},mult_c5_sum6};
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reg signed [32:0] mult_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_sum <= 'h0;
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else
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mult_sum <= -{{10{mult_c0_sum[22]}},mult_c0_sum} + {{8{mult_c1_sum[24]}},mult_c1_sum} - {{5{mult_c2_sum[27]}},mult_c2_sum} + {{4{mult_c3_sum[28]}},mult_c3_sum} - {{3{mult_c4_sum[29]}},mult_c4_sum} + {{1{mult_c5_sum[31]}},mult_c5_sum};
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wire signed [17:0] dout0_w;
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reg signed [15:0] dout0;
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assign dout0_w = mult_sum[32:15]+mult_sum[14];
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always@(posedge clk or negedge rstn)
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if(!rstn)
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dout0 <= 'h0;
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else if(dout0_w[16:15]==2'b01)
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dout0 <= 16'd32767;
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else if(dout0_w[16:15]==2'b10)
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dout0 <= -16'd32768;
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else
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dout0 <= dout0_w[15:0];
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assign dout = dout0;
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endmodule
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