179 lines
3.5 KiB
Verilog
179 lines
3.5 KiB
Verilog
module DUC_HB1_TOP (clkl,
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rstn,
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din,
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dout_p0,
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dout_p1
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);
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input clkl,rstn;
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input [15:0] din;
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output [15:0] dout_p0;
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output [15:0] dout_p1;
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reg [15:0] din_r1;
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reg [15:0] din_r2;
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reg [15:0] din_r3;
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reg [15:0] din_r4;
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reg [15:0] din_r5;
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reg [15:0] din_r6;
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reg [15:0] din_r7;
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reg [15:0] din_r8;
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reg [15:0] din_r9;
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reg [15:0] din_r10;
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reg [15:0] din_r11;
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reg [15:0] din_r12;
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reg [15:0] din_r13;
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reg [15:0] din_r14;
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reg [15:0] din_r15;
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reg [15:0] din_r16;
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reg [15:0] din_r17;
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reg [15:0] din_r18;
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reg [15:0] din_r19;
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reg [15:0] din_r20;
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reg [15:0] din_r21;
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reg [15:0] din_r22;
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reg [15:0] din_r23;
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reg [15:0] din_r24;
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reg [15:0] din_r25;
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reg [15:0] din_r26;
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reg [15:0] din_r27;
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reg [15:0] din_r28;
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reg [15:0] din_r29;
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reg [15:0] din_r30;
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reg [15:0] din_r31;
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reg [15:0] din_r32;
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reg [15:0] din_r33;
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reg [15:0] din_r34;
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reg [15:0] din_r35;
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always@(posedge clkl or negedge rstn)
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if(!rstn)
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begin
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din_r1 <= 'b0;
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din_r2 <= 'b0;
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din_r3 <= 'b0;
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din_r4 <= 'b0;
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din_r5 <= 'b0;
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din_r6 <= 'b0;
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din_r7 <= 'b0;
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din_r8 <= 'b0;
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din_r9 <= 'b0;
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din_r10 <= 'b0;
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din_r11 <= 'b0;
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din_r12 <= 'b0;
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din_r13 <= 'b0;
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din_r14 <= 'b0;
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din_r15 <= 'b0;
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din_r16 <= 'b0;
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din_r17 <= 'b0;
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din_r18 <= 'b0;
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din_r19 <= 'b0;
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din_r20 <= 'b0;
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din_r21 <= 'b0;
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din_r22 <= 'b0;
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din_r23 <= 'b0;
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din_r24 <= 'b0;
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din_r25 <= 'b0;
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din_r26 <= 'b0;
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din_r27 <= 'b0;
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din_r28 <= 'b0;
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din_r29 <= 'b0;
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din_r30 <= 'b0;
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din_r31 <= 'b0;
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din_r32 <= 'b0;
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din_r33 <= 'b0;
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din_r34 <= 'b0;
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din_r35 <= 'b0;
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end
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else
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begin
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din_r1 <= din;
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din_r2 <= din_r1;
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din_r3 <= din_r2;
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din_r4 <= din_r3;
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din_r5 <= din_r4;
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din_r6 <= din_r5;
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din_r7 <= din_r6;
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din_r8 <= din_r7;
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din_r9 <= din_r8;
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din_r10 <= din_r9;
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din_r11 <= din_r10;
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din_r12 <= din_r11;
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din_r13 <= din_r12;
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din_r14 <= din_r13;
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din_r15 <= din_r14;
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din_r16 <= din_r15;
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din_r17 <= din_r16;
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din_r18 <= din_r17;
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din_r19 <= din_r18;
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din_r20 <= din_r19;
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din_r21 <= din_r20;
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din_r22 <= din_r21;
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din_r23 <= din_r22;
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din_r24 <= din_r23;
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din_r25 <= din_r24;
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din_r26 <= din_r25;
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din_r27 <= din_r26;
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din_r28 <= din_r27;
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din_r29 <= din_r28;
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din_r30 <= din_r29;
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din_r31 <= din_r30;
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din_r32 <= din_r31;
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din_r33 <= din_r32;
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din_r34 <= din_r33;
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din_r35 <= din_r34;
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end
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DUC_HB1 inst_duc_hb1(
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.clk (clkl),
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.rstn (rstn),
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.din_0 (din),
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.din_1 (din_r1),
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.din_2 (din_r2),
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.din_3 (din_r3),
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.din_4 (din_r4),
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.din_5 (din_r5),
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.din_6 (din_r6),
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.din_7 (din_r7),
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.din_8 (din_r8),
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.din_9 (din_r9),
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.din_10 (din_r10),
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.din_11 (din_r11),
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.din_12 (din_r12),
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.din_13 (din_r13),
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.din_14 (din_r14),
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.din_15 (din_r15),
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.din_16 (din_r16),
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.din_17 (din_r17),
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.din_18 (din_r18),
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.din_19 (din_r19),
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.din_20 (din_r20),
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.din_21 (din_r21),
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.din_22 (din_r22),
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.din_23 (din_r23),
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.din_24 (din_r24),
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.din_25 (din_r25),
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.din_26 (din_r26),
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.din_27 (din_r27),
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.din_28 (din_r28),
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.din_29 (din_r29),
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.din_30 (din_r30),
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.din_31 (din_r31),
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.din_32 (din_r32),
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.din_33 (din_r33),
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.din_34 (din_r34),
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.din_35 (din_r35),
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.dout (dout_p1)
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);
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assign dout_p0 = din_r22;
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endmodule
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