596 lines
17 KiB
Verilog
596 lines
17 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : duc_hb1_shift.v
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// Department :
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// Author :
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.8 2024-03-26 thfu add pipeline
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module DUC_HB1 (
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clk,
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rstn,
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din_0,
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din_1,
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din_2,
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din_3,
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din_4,
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din_5,
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din_6,
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din_7,
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din_8,
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din_9,
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din_10,
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din_11,
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din_12,
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din_13,
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din_14,
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din_15,
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din_16,
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din_17,
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din_18,
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din_19,
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din_20,
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din_21,
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din_22,
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din_23,
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din_24,
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din_25,
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din_26,
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din_27,
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din_28,
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din_29,
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din_30,
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din_31,
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din_32,
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din_33,
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din_34,
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din_35,
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dout
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);
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input clk;
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input rstn;
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input signed [15:0] din_0;
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input signed [15:0] din_1;
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input signed [15:0] din_2;
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input signed [15:0] din_3;
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input signed [15:0] din_4;
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input signed [15:0] din_5;
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input signed [15:0] din_6;
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input signed [15:0] din_7;
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input signed [15:0] din_8;
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input signed [15:0] din_9;
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input signed [15:0] din_10;
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input signed [15:0] din_11;
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input signed [15:0] din_12;
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input signed [15:0] din_13;
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input signed [15:0] din_14;
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input signed [15:0] din_15;
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input signed [15:0] din_16;
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input signed [15:0] din_17;
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input signed [15:0] din_18;
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input signed [15:0] din_19;
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input signed [15:0] din_20;
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input signed [15:0] din_21;
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input signed [15:0] din_22;
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input signed [15:0] din_23;
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input signed [15:0] din_24;
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input signed [15:0] din_25;
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input signed [15:0] din_26;
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input signed [15:0] din_27;
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input signed [15:0] din_28;
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input signed [15:0] din_29;
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input signed [15:0] din_30;
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input signed [15:0] din_31;
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input signed [15:0] din_32;
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input signed [15:0] din_33;
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input signed [15:0] din_34;
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input signed [15:0] din_35;
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output signed [15:0] dout;
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parameter c0 = -20'd28;
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parameter c1 = 20'd82;
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parameter c2 = -20'd194;
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parameter c3 = 20'd397;
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parameter c4 = -20'd737;
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parameter c5 = 20'd1275;
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parameter c6 = -20'd2084;
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parameter c7 = 20'd3258;
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parameter c8 = -20'd4910;
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parameter c9 = 20'd7184;
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parameter c10 = -20'd10274;
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parameter c11 = 20'd14457;
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parameter c12 = -20'd20187;
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parameter c13 = 20'd28286;
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parameter c14 = -20'd40513;
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parameter c15 = 20'd61451;
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parameter c16 = -20'd108000;
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parameter c17 = 20'd332673;
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reg signed [16:0] sum_0_35;
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reg signed [16:0] sum_1_34;
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reg signed [16:0] sum_2_33;
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reg signed [16:0] sum_3_32;
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reg signed [16:0] sum_4_31;
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reg signed [16:0] sum_5_30;
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reg signed [16:0] sum_6_29;
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reg signed [16:0] sum_7_28;
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reg signed [16:0] sum_8_27;
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reg signed [16:0] sum_9_26;
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reg signed [16:0] sum_10_25;
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reg signed [16:0] sum_11_24;
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reg signed [16:0] sum_12_23;
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reg signed [16:0] sum_13_22;
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reg signed [16:0] sum_14_21;
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reg signed [16:0] sum_15_20;
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reg signed [16:0] sum_16_19;
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reg signed [16:0] sum_17_18;
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always@(posedge clk or negedge rstn) begin
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if(!rstn) begin
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sum_0_35 <= 'h0;
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sum_1_34 <= 'h0;
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sum_2_33 <= 'h0;
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sum_3_32 <= 'h0;
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sum_4_31 <= 'h0;
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sum_5_30 <= 'h0;
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sum_6_29 <= 'h0;
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sum_7_28 <= 'h0;
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sum_8_27 <= 'h0;
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sum_9_26 <= 'h0;
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sum_10_25 <= 'h0;
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sum_11_24 <= 'h0;
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sum_12_23 <= 'h0;
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sum_13_22 <= 'h0;
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sum_14_21 <= 'h0;
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sum_15_20 <= 'h0;
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sum_16_19 <= 'h0;
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sum_17_18 <= 'h0;
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end
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else begin
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sum_0_35 <= {{1 {din_0[15]}},din_0} + {{1 {din_35[15]}},din_35};
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sum_1_34 <= {{1 {din_1[15]}},din_1} + {{1 {din_34[15]}},din_34};
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sum_2_33 <= {{1 {din_2[15]}},din_2} + {{1 {din_33[15]}},din_33};
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sum_3_32 <= {{1 {din_3[15]}},din_3} + {{1 {din_32[15]}},din_32};
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sum_4_31 <= {{1 {din_4[15]}},din_4} + {{1 {din_31[15]}},din_31};
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sum_5_30 <= {{1 {din_5[15]}},din_5} + {{1 {din_30[15]}},din_30};
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sum_6_29 <= {{1 {din_6[15]}},din_6} + {{1 {din_29[15]}},din_29};
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sum_7_28 <= {{1 {din_7[15]}},din_7} + {{1 {din_28[15]}},din_28};
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sum_8_27 <= {{1 {din_8[15]}},din_8} + {{1 {din_27[15]}},din_27};
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sum_9_26 <= {{1 {din_9[15]}},din_9} + {{1 {din_26[15]}},din_26};
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sum_10_25 <= {{1 {din_10[15]}},din_10} + {{1 {din_25[15]}},din_25};
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sum_11_24 <= {{1 {din_11[15]}},din_11} + {{1 {din_24[15]}},din_24};
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sum_12_23 <= {{1 {din_12[15]}},din_12} + {{1 {din_23[15]}},din_23};
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sum_13_22 <= {{1 {din_13[15]}},din_13} + {{1 {din_22[15]}},din_22};
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sum_14_21 <= {{1 {din_14[15]}},din_14} + {{1 {din_21[15]}},din_21};
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sum_15_20 <= {{1 {din_15[15]}},din_15} + {{1 {din_20[15]}},din_20};
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sum_16_19 <= {{1 {din_16[15]}},din_16} + {{1 {din_19[15]}},din_19};
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sum_17_18 <= {{1 {din_17[15]}},din_17} + {{1 {din_18[15]}},din_18};
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end
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end
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wire signed [17:0] mult_c0_sum0;
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assign mult_c0_sum0 = {sum_0_35,1'b0};
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reg signed [17:0] mult_c0_sum;
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always@(posedge clk or negedge rstn) begin
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if(!rstn)
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mult_c0_sum <= 'h0;
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else
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mult_c0_sum <= mult_c0_sum0;
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end
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wire signed [16:0] mult_c1_sum0;
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wire signed [18:0] mult_c1_sum1;
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assign mult_c1_sum0 = sum_1_34;
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assign mult_c1_sum1 = {sum_1_34,2'b0};
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reg signed [19:0] mult_c1_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c1_sum <= 'h0;
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else
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mult_c1_sum <= {{3{mult_c1_sum0[16]}},mult_c1_sum0} + {{1{mult_c1_sum1[18]}},mult_c1_sum1};
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wire signed [18:0] mult_c2_sum0;
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wire signed [19:0] mult_c2_sum1;
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assign mult_c2_sum0 = {sum_2_33,2'b0};
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assign mult_c2_sum1 = {sum_2_33,3'b0};
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reg signed [20:0] mult_c2_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c2_sum <= 'h0;
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else
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mult_c2_sum <= {{2{mult_c2_sum0[18]}},mult_c2_sum0} + {{1{mult_c2_sum1[19]}},mult_c2_sum1};
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wire signed [16:0] mult_c3_sum0;
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wire signed [19:0] mult_c3_sum1;
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wire signed [20:0] mult_c3_sum2;
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assign mult_c3_sum0 = sum_3_32;
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assign mult_c3_sum1 = {sum_3_32,3'b0};
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assign mult_c3_sum2 = {sum_3_32,4'b0};
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reg signed [21:0] mult_c3_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c3_sum <= 'h0;
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else
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mult_c3_sum <= {{5{mult_c3_sum0[16]}},mult_c3_sum0} + {{2{mult_c3_sum1[19]}},mult_c3_sum1} + {{1{mult_c3_sum2[20]}},mult_c3_sum2};
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wire signed [17:0] mult_c4_sum0;
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wire signed [20:0] mult_c4_sum1;
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wire signed [21:0] mult_c4_sum2;
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assign mult_c4_sum0 = {sum_4_31,1'b0};
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assign mult_c4_sum1 = {sum_4_31,4'b0};
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assign mult_c4_sum2 = {sum_4_31,5'b0};
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reg signed [22:0] mult_c4_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c4_sum <= 'h0;
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else
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mult_c4_sum <= - {{5{mult_c4_sum0[17]}},mult_c4_sum0} + {{2{mult_c4_sum1[20]}},mult_c4_sum1} + {{1{mult_c4_sum2[21]}},mult_c4_sum2};
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wire signed [20:0] mult_c5_sum0;
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wire signed [21:0] mult_c5_sum1;
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wire signed [23:0] mult_c5_sum2;
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assign mult_c5_sum0 = {sum_5_30,4'b0};
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assign mult_c5_sum1 = {sum_5_30,5'b0};
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assign mult_c5_sum2 = {sum_5_30,7'b0};
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reg signed [24:0] mult_c5_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c5_sum <= 'h0;
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else
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mult_c5_sum <= -{{4{mult_c5_sum0[20]}},mult_c5_sum0} - {{3{mult_c5_sum1[21]}},mult_c5_sum1} + {{1{mult_c5_sum2[23]}},mult_c5_sum2};
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wire signed [17:0] mult_c6_sum0;
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wire signed [23:0] mult_c6_sum1;
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assign mult_c6_sum0 = {sum_6_29,1'b0};
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assign mult_c6_sum1 = {sum_6_29,7'b0};
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reg signed [24:0] mult_c6_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c6_sum <= 'h0;
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else
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mult_c6_sum <= {{7{mult_c6_sum0[17]}},mult_c6_sum0} + {{1{mult_c6_sum1[23]}},mult_c6_sum1};
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wire signed [18:0] mult_c7_sum0;
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wire signed [20:0] mult_c7_sum1;
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wire signed [21:0] mult_c7_sum2;
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wire signed [24:0] mult_c7_sum3;
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assign mult_c7_sum0 = {sum_7_28,2'b0};
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assign mult_c7_sum1 = {sum_7_28,4'b0};
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assign mult_c7_sum2 = {sum_7_28,5'b0};
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assign mult_c7_sum3 = {sum_7_28,8'b0};
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reg signed [25:0] mult_c7_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c7_sum <= 'h0;
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else
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mult_c7_sum <= -{{7{mult_c7_sum0[18]}},mult_c7_sum0} - {{5{mult_c7_sum1[20]}},mult_c7_sum1} - {{4{mult_c7_sum2[21]}},mult_c7_sum2} + {{1{mult_c7_sum3[24]}},mult_c7_sum3};
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wire signed [16:0] mult_c8_sum0;
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wire signed [17:0] mult_c8_sum1;
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wire signed [20:0] mult_c8_sum2;
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wire signed [21:0] mult_c8_sum3;
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wire signed [24:0] mult_c8_sum4;
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assign mult_c8_sum0 = sum_8_27;
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assign mult_c8_sum1 = {sum_8_27,1'b0};
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assign mult_c8_sum2 = {sum_8_27,4'b0};
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assign mult_c8_sum3 = {sum_8_27,5'b0};
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assign mult_c8_sum4 = {sum_8_27,8'b0};
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reg signed [25:0] mult_c8_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c8_sum <= 'h0;
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else
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mult_c8_sum <= {{9{mult_c8_sum0[16]}},mult_c8_sum0} + {{8{mult_c8_sum1[17]}},mult_c8_sum1} + {{5{mult_c8_sum2[20]}},mult_c8_sum2} + {{4{mult_c8_sum3[21]}},mult_c8_sum3} + {{1{mult_c8_sum4[24]}},mult_c8_sum4};
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wire signed [16:0] mult_c9_sum0;
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wire signed [22:0] mult_c9_sum1;
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wire signed [25:0] mult_c9_sum2;
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assign mult_c9_sum0 = sum_9_26;
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assign mult_c9_sum1 = {sum_9_26,6'b0};
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assign mult_c9_sum2 = {sum_9_26,9'b0};
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reg signed [26:0] mult_c9_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c9_sum <= 'h0;
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else
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mult_c9_sum <= {{10{mult_c9_sum0[16]}},mult_c9_sum0} - {{4{mult_c9_sum1[22]}},mult_c9_sum1} + {{1{mult_c9_sum2[25]}},mult_c9_sum2};
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wire signed [17:0] mult_c10_sum0;
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wire signed [23:0] mult_c10_sum1;
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wire signed [25:0] mult_c10_sum2;
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assign mult_c10_sum0 = {sum_10_25,1'b0};
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assign mult_c10_sum1 = {sum_10_25,7'b0};
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assign mult_c10_sum2 = {sum_10_25,9'b0};
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reg signed [26:0] mult_c10_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c10_sum <= 'h0;
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else
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mult_c10_sum <= {{9{mult_c10_sum0[17]}},mult_c10_sum0} + {{3{mult_c10_sum1[23]}},mult_c10_sum1} + {{1{mult_c10_sum2[25]}},mult_c10_sum2};
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wire signed [19:0] mult_c11_sum0;
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wire signed [23:0] mult_c11_sum1;
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wire signed [26:0] mult_c11_sum2;
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assign mult_c11_sum0 = {sum_11_24,3'b0};
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assign mult_c11_sum1 = {sum_11_24,7'b0};
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assign mult_c11_sum2 = {sum_11_24,10'b0};
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reg signed [27:0] mult_c11_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c11_sum <= 'h0;
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else
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mult_c11_sum <= {{8{mult_c11_sum0[19]}},mult_c11_sum0} - {{4{mult_c11_sum1[23]}},mult_c11_sum1} + {{1{mult_c11_sum2[26]}},mult_c11_sum2};
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wire signed [17:0] mult_c12_sum0;
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wire signed [20:0] mult_c12_sum1;
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wire signed [24:0] mult_c12_sum2;
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wire signed [25:0] mult_c12_sum3;
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wire signed [27:0] mult_c12_sum4;
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assign mult_c12_sum0 = {sum_12_23,1'b0};
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assign mult_c12_sum1 = {sum_12_23,4'b0};
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assign mult_c12_sum2 = {sum_12_23,8'b0};
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assign mult_c12_sum3 = {sum_12_23,9'b0};
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assign mult_c12_sum4 = {sum_12_23,11'b0};
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reg signed [28:0] mult_c12_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c12_sum <= 'h0;
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else
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mult_c12_sum <= - {{11{mult_c12_sum0[17]}},mult_c12_sum0} - {{8{mult_c12_sum1[20]}},mult_c12_sum1} - {{4{mult_c12_sum2[24]}},mult_c12_sum2} - {{3{mult_c12_sum3[25]}},mult_c12_sum3} + {{1{mult_c12_sum4[27]}},mult_c12_sum4};
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wire signed [19:0] mult_c13_sum0;
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wire signed [20:0] mult_c13_sum1;
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wire signed [24:0] mult_c13_sum2;
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wire signed [27:0] mult_c13_sum3;
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assign mult_c13_sum0 = {sum_13_22,3'b0};
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assign mult_c13_sum1 = {sum_13_22,4'b0};
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assign mult_c13_sum2 = {sum_13_22,8'b0};
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assign mult_c13_sum3 = {sum_13_22,11'b0};
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reg signed [28:0] mult_c13_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c13_sum <= 'h0;
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else
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mult_c13_sum <= - {{9{mult_c13_sum0[19]}},mult_c13_sum0} - {{8{mult_c13_sum1[20]}},mult_c13_sum1} - {{4{mult_c13_sum2[24]}},mult_c13_sum2} + {{1{mult_c13_sum3[27]}},mult_c13_sum3};
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wire signed [18:0] mult_c14_sum0;
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wire signed [21:0] mult_c14_sum1;
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wire signed [25:0] mult_c14_sum2;
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wire signed [27:0] mult_c14_sum3;
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assign mult_c14_sum0 = {sum_14_21,2'b0};
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assign mult_c14_sum1 = {sum_14_21,5'b0};
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assign mult_c14_sum2 = {sum_14_21,9'b0};
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assign mult_c14_sum3 = {sum_14_21,11'b0};
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reg signed [28:0] mult_c14_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c14_sum <= 'h0;
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else
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mult_c14_sum <= {{10{mult_c14_sum0[18]}},mult_c14_sum0} - {{7{mult_c14_sum1[21]}},mult_c14_sum1} + {{3{mult_c14_sum2[25]}},mult_c14_sum2} + {{1{mult_c14_sum3[27]}},mult_c14_sum3};
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wire signed [16:0] mult_c15_sum0;
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wire signed [24:0] mult_c15_sum1;
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wire signed [28:0] mult_c15_sum2;
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assign mult_c15_sum0 = sum_15_20;
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assign mult_c15_sum1 = {sum_15_20,8'b0};
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assign mult_c15_sum2 = {sum_15_20,12'b0};
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reg signed [29:0] mult_c15_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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mult_c15_sum <= 'h0;
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else
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mult_c15_sum <= {{13{mult_c15_sum0[16]}},mult_c15_sum0} - {{5{mult_c15_sum1[24]}},mult_c15_sum1} + {{1{mult_c15_sum2[28]}},mult_c15_sum2};
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wire signed [17:0] mult_c16_sum0;
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wire signed [21:0] mult_c16_sum1;
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wire signed [22:0] mult_c16_sum2;
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wire signed [25:0] mult_c16_sum3;
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wire signed [27:0] mult_c16_sum4;
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wire signed [28:0] mult_c16_sum5;
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assign mult_c16_sum0 = {sum_16_19,1'b0};
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assign mult_c16_sum1 = {sum_16_19,5'b0};
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assign mult_c16_sum2 = {sum_16_19,6'b0};
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assign mult_c16_sum3 = {sum_16_19,9'b0};
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assign mult_c16_sum4 = {sum_16_19,11'b0};
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assign mult_c16_sum5 = {sum_16_19,12'b0};
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reg signed [29:0] mult_c16_sum;
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always@(posedge clk or negedge rstn)
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if(!rstn)
|
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mult_c16_sum <= 'h0;
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else
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mult_c16_sum <= -{{12{mult_c16_sum0[17]}},mult_c16_sum0} + {{8{mult_c16_sum1[21]}},mult_c16_sum1} + {{7{mult_c16_sum2[22]}},mult_c16_sum2} + {{4{mult_c16_sum3[25]}},mult_c16_sum3} + {{2{mult_c16_sum4[27]}},mult_c16_sum4} + {{1{mult_c16_sum5[28]}},mult_c16_sum5};
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wire signed [19:0] mult_c17_sum0;
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wire signed [22:0] mult_c17_sum1;
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wire signed [24:0] mult_c17_sum2;
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wire signed [28:0] mult_c17_sum3;
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wire signed [30:0] mult_c17_sum4;
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assign mult_c17_sum0 = {sum_17_18,3'b0};
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assign mult_c17_sum1 = {sum_17_18,6'b0};
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assign mult_c17_sum2 = {sum_17_18,8'b0};
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assign mult_c17_sum3 = {sum_17_18,12'b0};
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assign mult_c17_sum4 = {sum_17_18,14'b0};
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reg signed [31:0] mult_c17_sum;
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always@(posedge clk or negedge rstn)
|
|
if(!rstn)
|
|
mult_c17_sum <= 'h0;
|
|
else
|
|
mult_c17_sum <= - {{12{mult_c17_sum0[19]}},mult_c17_sum0} + {{9{mult_c17_sum1[22]}},mult_c17_sum1} + {{7{mult_c17_sum2[24]}},mult_c17_sum2} + {{3{mult_c17_sum3[28]}},mult_c17_sum3} + {{1{mult_c17_sum4[30]}},mult_c17_sum4};
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reg signed [22:0] mult_sum_r1;
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reg signed [27:0] mult_sum_r2;
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reg signed [30:0] mult_sum_r3;
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reg signed [32:0] mult_sum_r4;
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always@(posedge clk or negedge rstn)
|
|
if(!rstn)
|
|
mult_sum_r1 <= 'h0;
|
|
else
|
|
mult_sum_r1 <= -{{5{mult_c0_sum[17]}},mult_c0_sum} + {{3{mult_c1_sum[19]}},mult_c1_sum} - {{2{mult_c2_sum[20]}},mult_c2_sum} + {{1{mult_c3_sum[21]}},mult_c3_sum};
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always@(posedge clk or negedge rstn)
|
|
if(!rstn)
|
|
mult_sum_r2 <= 'h0;
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|
else
|
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mult_sum_r2 <= -{{5{mult_c4_sum[22]}},mult_c4_sum} + {{3{mult_c5_sum[24]}},mult_c5_sum} - {{3{mult_c6_sum[24]}},mult_c6_sum} + {{2{mult_c7_sum[25]}},mult_c7_sum};
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|
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|
always@(posedge clk or negedge rstn)
|
|
if(!rstn)
|
|
mult_sum_r3 <= 'h0;
|
|
else
|
|
mult_sum_r3 <= -{{5{mult_c8_sum[25]}},mult_c8_sum} + {{4{mult_c9_sum[26]}},mult_c9_sum} - {{4{mult_c10_sum[26]}},mult_c10_sum} + {{3{mult_c11_sum[27]}},mult_c11_sum} - {{2{mult_c12_sum[28]}},mult_c12_sum};
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|
|
|
always@(posedge clk or negedge rstn)
|
|
if(!rstn)
|
|
mult_sum_r4 <= 'h0;
|
|
else
|
|
mult_sum_r4 <= {{4{mult_c13_sum[28]}},mult_c13_sum} - {{4{mult_c14_sum[28]}},mult_c14_sum} + {{3{mult_c15_sum[29]}},mult_c15_sum} - {{3{mult_c16_sum[29]}},mult_c16_sum} + {{1{mult_c17_sum[31]}},mult_c17_sum};
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|
|
|
reg signed [33:0] mult_sum;
|
|
|
|
always@(posedge clk or negedge rstn)
|
|
if(!rstn)
|
|
mult_sum <= 'h0;
|
|
else
|
|
mult_sum <= mult_sum_r1 + mult_sum_r2 + mult_sum_r3 + mult_sum_r4;
|
|
|
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|
|
reg signed [15:0] dout0;
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|
|
|
wire [19:0] dout0_w;
|
|
|
|
assign dout0_w = mult_sum[33:15] + mult_sum[14];
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|
|
|
always@(posedge clk or negedge rstn)
|
|
if(!rstn)
|
|
dout0 <= 'h0;
|
|
else if(dout0_w[16:15]==2'b01)
|
|
dout0 <= 16'd32767;
|
|
else if(dout0_w[16:15]==2'b10)
|
|
dout0 <= -16'd32768;
|
|
else
|
|
dout0 <= dout0_w[15:0];
|
|
|
|
assign dout = dout0;
|
|
|
|
|
|
endmodule
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