322 lines
7.3 KiB
Verilog
322 lines
7.3 KiB
Verilog
module DUC4(
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input clkl
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,input rstn
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,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16;
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,input dsp_alwayson
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,input data_vldi
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,input [15:0] din
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,output [15:0] dout_p0
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,output [15:0] dout_p1
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,output [15:0] dout_p2
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,output [15:0] dout_p3
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,output [15:0] dout_p4
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,output [15:0] dout_p5
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,output [15:0] dout_p6
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,output [15:0] dout_p7
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,output [15:0] dout_p8
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,output [15:0] dout_p9
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,output [15:0] dout_pa
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,output [15:0] dout_pb
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,output [15:0] dout_pc
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,output [15:0] dout_pd
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,output [15:0] dout_pe
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,output [15:0] dout_pf
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,output data_vldo
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);
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wire [15:0] dt1_p_0;
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wire [15:0] dt1_p_1;
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wire [15:0] dt2_p_0;
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wire [15:0] dt2_p_1;
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wire [15:0] dt2_p_2;
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wire [15:0] dt2_p_3;
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wire [15:0] dt3_p_0;
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wire [15:0] dt3_p_1;
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wire [15:0] dt3_p_2;
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wire [15:0] dt3_p_3;
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wire [15:0] dt3_p_4;
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wire [15:0] dt3_p_5;
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wire [15:0] dt3_p_6;
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wire [15:0] dt3_p_7;
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wire [15:0] dt4_p_0;
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wire [15:0] dt4_p_1;
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wire [15:0] dt4_p_2;
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wire [15:0] dt4_p_3;
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wire [15:0] dt4_p_4;
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wire [15:0] dt4_p_5;
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wire [15:0] dt4_p_6;
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wire [15:0] dt4_p_7;
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wire [15:0] dt4_p_8;
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wire [15:0] dt4_p_9;
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wire [15:0] dt4_p_a;
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wire [15:0] dt4_p_b;
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wire [15:0] dt4_p_c;
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wire [15:0] dt4_p_d;
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wire [15:0] dt4_p_e;
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wire [15:0] dt4_p_f;
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reg [15:0] mux_p_0;
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reg [15:0] mux_p_1;
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reg [15:0] mux_p_2;
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reg [15:0] mux_p_3;
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reg [15:0] mux_p_4;
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reg [15:0] mux_p_5;
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reg [15:0] mux_p_6;
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reg [15:0] mux_p_7;
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reg [15:0] mux_p_8;
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reg [15:0] mux_p_9;
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reg [15:0] mux_p_a;
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reg [15:0] mux_p_b;
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reg [15:0] mux_p_c;
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reg [15:0] mux_p_d;
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reg [15:0] mux_p_e;
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reg [15:0] mux_p_f;
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reg [70:0] DUC4_data_vld_r;
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always@(posedge clkl or negedge rstn)
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if(!rstn)
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begin
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DUC4_data_vld_r <= 9'b0;
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end
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else
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begin
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DUC4_data_vld_r <= {DUC4_data_vld_r[70:0], data_vldi};
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end
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///////////////////////////////////////////////////////
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//DUC_HB1_TOP inst
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///////////////////////////////////////////////////////
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DUC_HB1_TOP U0_DUC_HB1_TOP (
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.clkl ( clkl )
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,.rstn ( rstn )
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,.din ( din )
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,.dout_p0 ( dt1_p_0 )
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,.dout_p1 ( dt1_p_1 )
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);
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///////////////////////////////////////////////////////
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//DUC_HB2_TOP_S inst1
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///////////////////////////////////////////////////////
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DUC_HB2_TOP_S U1_DUC_HB2_TOP (
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.clkl ( clkl )
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,.rstn ( rstn )
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,.din0 ( dt1_p_1 )
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,.din1 ( dt1_p_0 )
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,.dout_p0 ( dt2_p_0 )
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,.dout_p1 ( dt2_p_1 )
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,.dout_p2 ( dt2_p_2 )
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,.dout_p3 ( dt2_p_3 )
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);
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///////////////////////////////////////////////////////
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//DUC_HB3_TOP_S2 inst1
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///////////////////////////////////////////////////////
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DUC_HB3_TOP_S2 U1_DUC_HB3_TOP (
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.clkl ( clkl )
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,.rstn ( rstn )
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,.din0 ( dt2_p_2 )
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,.din1 ( dt2_p_3 )
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,.din2 ( dt2_p_0 )
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,.din3 ( dt2_p_1 )
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,.dout_p0 ( dt3_p_0 )
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,.dout_p1 ( dt3_p_1 )
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,.dout_p2 ( dt3_p_2 )
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,.dout_p3 ( dt3_p_3 )
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,.dout_p4 ( dt3_p_4 )
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,.dout_p5 ( dt3_p_5 )
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,.dout_p6 ( dt3_p_6 )
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,.dout_p7 ( dt3_p_7 )
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);
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///////////////////////////////////////////////////////
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//DUC_HB4_TOP_S3 inst1
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///////////////////////////////////////////////////////
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DUC_HB4_TOP_S3 U1_DUC_HB4_TOP (
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.clkl ( clkl )
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,.rstn ( rstn )
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,.din0 ( dt3_p_6 )
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,.din1 ( dt3_p_7 )
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,.din2 ( dt3_p_4 )
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,.din3 ( dt3_p_5 )
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,.din4 ( dt3_p_2 )
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,.din5 ( dt3_p_3 )
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,.din6 ( dt3_p_0 )
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,.din7 ( dt3_p_1 )
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,.dout_p0 ( dt4_p_0 )
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,.dout_p1 ( dt4_p_1 )
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,.dout_p2 ( dt4_p_2 )
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,.dout_p3 ( dt4_p_3 )
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,.dout_p4 ( dt4_p_4 )
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,.dout_p5 ( dt4_p_5 )
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,.dout_p6 ( dt4_p_6 )
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,.dout_p7 ( dt4_p_7 )
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,.dout_p8 ( dt4_p_8 )
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,.dout_p9 ( dt4_p_9 )
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,.dout_pa ( dt4_p_a )
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,.dout_pb ( dt4_p_b )
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,.dout_pc ( dt4_p_c )
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,.dout_pd ( dt4_p_d )
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,.dout_pe ( dt4_p_e )
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,.dout_pf ( dt4_p_f )
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);
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always@(posedge clkl) begin
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case(intp_mode)
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3'b000 : begin
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mux_p_0 <= din;
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mux_p_1 <= 16'h0;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= 16'h0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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mux_p_8 <= 16'h0;
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mux_p_9 <= 16'h0;
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mux_p_a <= 16'h0;
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mux_p_b <= 16'h0;
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mux_p_c <= 16'h0;
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mux_p_d <= 16'h0;
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mux_p_e <= 16'h0;
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mux_p_f <= 16'h0;
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end
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3'b001 : begin
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mux_p_0 <= dt1_p_0;
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mux_p_1 <= 16'h0;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= 16'h0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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mux_p_8 <= dt1_p_1;
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mux_p_9 <= 16'h0;
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mux_p_a <= 16'h0;
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mux_p_b <= 16'h0;
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mux_p_c <= 16'h0;
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mux_p_d <= 16'h0;
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mux_p_e <= 16'h0;
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mux_p_f <= 16'h0;
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end
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3'b010 : begin
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mux_p_0 <= dt2_p_1;
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mux_p_1 <= 16'h0;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= dt2_p_0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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mux_p_8 <= dt2_p_3;
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mux_p_9 <= 16'h0;
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mux_p_a <= 16'h0;
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mux_p_b <= 16'h0;
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mux_p_c <= dt2_p_2;
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mux_p_d <= 16'h0;
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mux_p_e <= 16'h0;
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mux_p_f <= 16'h0;
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end
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3'b011 : begin
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mux_p_0 <= dt3_p_1;
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mux_p_1 <= 16'h0;
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mux_p_2 <= dt3_p_0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= dt3_p_3;
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mux_p_5 <= 16'h0;
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mux_p_6 <= dt3_p_2;
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mux_p_7 <= 16'h0;
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mux_p_8 <= dt3_p_5;
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mux_p_9 <= 16'h0;
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mux_p_a <= dt3_p_4;
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mux_p_b <= 16'h0;
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mux_p_c <= dt3_p_7;
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mux_p_d <= 16'h0;
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mux_p_e <= dt3_p_6;
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mux_p_f <= 16'h0;
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end
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3'b100 : begin
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mux_p_0 <= dt4_p_1;
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mux_p_1 <= dt4_p_0;
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mux_p_2 <= dt4_p_3;
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mux_p_3 <= dt4_p_2;
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mux_p_4 <= dt4_p_5;
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mux_p_5 <= dt4_p_4;
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mux_p_6 <= dt4_p_7;
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mux_p_7 <= dt4_p_6;
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mux_p_8 <= dt4_p_9;
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mux_p_9 <= dt4_p_8;
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mux_p_a <= dt4_p_b;
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mux_p_b <= dt4_p_a;
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mux_p_c <= dt4_p_d;
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mux_p_d <= dt4_p_c;
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mux_p_e <= dt4_p_f;
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mux_p_f <= dt4_p_e;
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end
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default : begin
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mux_p_0 <= 16'h0;
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mux_p_1 <= 16'h0;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= 16'h0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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mux_p_8 <= 16'h0;
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mux_p_9 <= 16'h0;
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mux_p_a <= 16'h0;
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mux_p_b <= 16'h0;
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mux_p_c <= 16'h0;
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mux_p_d <= 16'h0;
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mux_p_e <= 16'h0;
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mux_p_f <= 16'h0;
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end
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endcase
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end
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assign dout_p0 = mux_p_f ;
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assign dout_p1 = mux_p_e ;
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assign dout_p2 = mux_p_d ;
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assign dout_p3 = mux_p_c ;
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assign dout_p4 = mux_p_b ;
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assign dout_p5 = mux_p_a ;
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assign dout_p6 = mux_p_9 ;
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assign dout_p7 = mux_p_8 ;
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assign dout_p8 = mux_p_7 ;
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assign dout_p9 = mux_p_6 ;
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assign dout_pa = mux_p_5 ;
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assign dout_pb = mux_p_4 ;
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assign dout_pc = mux_p_3 ;
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assign dout_pd = mux_p_2 ;
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assign dout_pe = mux_p_1 ;
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assign dout_pf = mux_p_0 ;
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reg data_vldo_t;
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always@(posedge clkl) begin
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if(dsp_alwayson) begin
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data_vldo_t <= 1'b1;
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end
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else begin
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case(intp_mode)
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3'b000 : data_vldo_t <= data_vldi;
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3'b001 : data_vldo_t <= DUC4_data_vld_r[21];
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3'b010 : data_vldo_t <= DUC4_data_vld_r[28];
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3'b011 : data_vldo_t <= DUC4_data_vld_r[33];
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3'b100 : data_vldo_t <= DUC4_data_vld_r[37];
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default : data_vldo_t <= data_vldi;
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endcase
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end
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end
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assign data_vldo = data_vldo_t;
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endmodule
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