1529 lines
94 KiB
Verilog
1529 lines
94 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : xyz_chip_top.v
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// Department :
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// Author : pwy
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 1.2 2024-04-16 pwy XYZ control the top-level module
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "../define/chip_define.v"
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module xyz_chip_top (
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// PAD Strat //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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input PI_async_rstn // hardware Reset, active low
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//sync
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,input PI_sync_in // Chip synchronization signal input, high pulse valid
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,output PO_sync_out // Chip synchronization signal output, high pulse valid
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//Feedback signal
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,input [1 :0] PI_ch0_feedback // Ch0 Feedback signals from the readout chip
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`ifdef CHANNEL_IS_FOUR
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,input [1 :0] PI_ch1_feedback // Ch1 Feedback signals from the readout chip
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,input [1 :0] PI_ch2_feedback // Ch2 Feedback signals from the readout chip
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,input [1 :0] PI_ch3_feedback // Ch3 Feedback signals from the readout chip
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`endif
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//config chip id
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,input [4 :0] PI_cfgid // During power-on initialization, the IO configuration
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// values are read as the chip ID number
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//spi port
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,input PI_sclk // Spi Clock
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,input PI_csn // Spi Chip Select active low
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,input PI_mosi // Spi Mosi
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,output PO_miso // Spi Miso
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//irq
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,output PO_irq // Interrupt signal in the chip, high level active
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// PAD End //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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//+++++++++++++++++++++++++++++++++++++++++++++//
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// PIN Strat //
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//+++++++++++++++++++++++++++++++++++++++++++++//
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//-------------------------clcok pin from pll-------------------------------------------------
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,input clk // System Main Clock
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//-------------------------Power on reset pin from por----------------------------------------
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,input por_rstn // Power on reset, active low
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//------------------------------digital IO----------------------------------------------------
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//------------------------------PLL cfg pin----------------------------------------------------
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,output ref_sel // Clock source selection for a frequency divider;
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// 1'b0:External clock source
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// 1'b1:internal phase-locked loop clock source
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,output ref_en // Input reference clock enable
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// 1'b0:enable,1'b1:disable
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,output ref_s2d_en // Referenced clock differential to single-ended conversion enable
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// 1'b0:enable,1'b1:disable
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,output [6 :0] p_cnt // P counter
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,output pfd_delay // PFD Dead Zone
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,output pfd_dff_Set // Setting the PFD register,active high
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,output pfd_dff_4and // PFD output polarity
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,output [3 :0] spd_div // SPD Frequency Divider
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,output spd_pulse_width // Pulse Width of SPD
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,output spd_pulse_sw // Pulse sw of SPD
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,output cpc_sel // current source selection
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,output [1 :0] swcp_i // PTAT current switch
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,output [3 :0] sw_ptat_r // PTAT current adjustment
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,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current
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,output sw_fll_delay // PLL Dead Zone
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,output pfd_sel // PFD Loop selection
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,output spd_sel // SPD Loop selection
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,output fll_sel // FLL Loop selection
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,output vco_tc // VCO temperature compensation
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,output vco_tcr // VCO temperature compensation resistor
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,output vco_gain_adj // VCO gain adjustment
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,output vco_gain_adj_r // VCO gain adjustment resistor
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,output [2 :0] vco_cur_adj // VCO current adjustment
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,output vco_buff_en // VCO buff enable,active high
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,output vco_en // VCO enable,active high
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,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment
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,output [6 :0] vco_fb_adj // VCO frequency band adjustment
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,output afc_en // AFC enable
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,output afc_shutdown // AFC module shutdown signal
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,output [0 :0] afc_det_speed // AFC detection speed
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,output [0 :0] flag_out_sel // Read and choose the signs
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,output afc_reset // AFC reset
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,output [10 :0] afc_cnt // AFC frequency band adjustment function counter
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// counting time adjustment
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,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection
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// feature counter
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,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator
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,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count
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,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band
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// adjustment function
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,output sync_clr // PLL div sync clr,low active
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,output pll_rstn // PLL reset,active low
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,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
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,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
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,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable
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,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
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,output clkrx_pdn // CLock Rx Power Down
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,input pll_lock // PLL LOCK
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//------------------------------Ch0 DAC cfg pin----------------------------------------------------
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,output [2 :0] ch0_dac_addr
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,output [2 :0] ch0_dac_dw
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,output [8 :0] ch0_dac_ref
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,output [16 :0] ch0_dac_Prbs_rst0
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,output [16 :0] ch0_dac_Prbs_set0
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,output [16 :0] ch0_dac_Prbs_rst1
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,output [16 :0] ch0_dac_Prbs_set1
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,output ch0_dac_Cal_sig
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,output ch0_dac_Cal_rstn
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,output ch0_dac_Cal_div_rstn
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,input ch0_dac_Cal_end
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`ifdef CHANNEL_IS_FOUR
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//------------------------------Ch1 DAC cfg pin----------------------------------------------------
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,output [2 :0] ch1_dac_addr
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,output [2 :0] ch1_dac_dw
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,output [8 :0] ch1_dac_ref
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,output [16 :0] ch1_dac_Prbs_rst0
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,output [16 :0] ch1_dac_Prbs_set0
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,output [16 :0] ch1_dac_Prbs_rst1
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,output [16 :0] ch1_dac_Prbs_set1
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,output ch1_dac_Cal_sig
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,output ch1_dac_Cal_rstn
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,output ch1_dac_Cal_div_rstn
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,output ch1_dac_Digitalclk
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,input ch1_dac_Cal_end
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//------------------------------Ch2 DAC cfg pin----------------------------------------------------
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,output [2 :0] ch2_dac_addr
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,output [2 :0] ch2_dac_dw
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,output [8 :0] ch2_dac_ref
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,output [16 :0] ch2_dac_Prbs_rst0
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,output [16 :0] ch2_dac_Prbs_set0
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,output [16 :0] ch2_dac_Prbs_rst1
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,output [16 :0] ch2_dac_Prbs_set1
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,output ch2_dac_Cal_sig
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,output ch2_dac_Cal_rstn
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,output ch2_dac_Cal_div_rstn
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,output ch2_dac_Digitalclk
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,input ch2_dac_Cal_end
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//------------------------------Ch3 DAC cfg pin----------------------------------------------------
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,output [2 :0] ch3_dac_addr
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,output [2 :0] ch3_dac_dw
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,output [8 :0] ch3_dac_ref
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,output [16 :0] ch3_dac_Prbs_rst0
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,output [16 :0] ch3_dac_Prbs_set0
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,output [16 :0] ch3_dac_Prbs_rst1
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,output [16 :0] ch3_dac_Prbs_set1
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,output ch3_dac_Cal_sig
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,output ch3_dac_Cal_rstn
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,output ch3_dac_Cal_div_rstn
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,output ch3_dac_Digitalclk
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,input ch3_dac_Cal_end
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`endif
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//------------------------------Ch0 DSP data out----------------------------------------------------
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`ifdef CHANNEL_XY_ON
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,output [14:0] ch0_xy_A_DEM_MSB_OUT0
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,output [14:0] ch0_xy_A_DEM_MSB_OUT1
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,output [14:0] ch0_xy_A_DEM_MSB_OUT2
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,output [14:0] ch0_xy_A_DEM_MSB_OUT3
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,output [14:0] ch0_xy_A_DEM_MSB_OUT4
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,output [14:0] ch0_xy_A_DEM_MSB_OUT5
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,output [14:0] ch0_xy_A_DEM_MSB_OUT6
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,output [14:0] ch0_xy_A_DEM_MSB_OUT7
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,output [14:0] ch0_xy_B_DEM_MSB_OUT0
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,output [14:0] ch0_xy_B_DEM_MSB_OUT1
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,output [14:0] ch0_xy_B_DEM_MSB_OUT2
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,output [14:0] ch0_xy_B_DEM_MSB_OUT3
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,output [14:0] ch0_xy_B_DEM_MSB_OUT4
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,output [14:0] ch0_xy_B_DEM_MSB_OUT5
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,output [14:0] ch0_xy_B_DEM_MSB_OUT6
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,output [14:0] ch0_xy_B_DEM_MSB_OUT7
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT0
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT1
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT2
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT3
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT4
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT5
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT6
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,output [6 :0] ch0_xy_A_DEM_ISB_OUT7
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT0
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT1
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT2
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT3
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT4
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT5
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT6
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,output [6 :0] ch0_xy_B_DEM_ISB_OUT7
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT0
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT1
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT2
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT3
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT4
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT5
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT6
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,output [8 :0] ch0_xy_A_DEM_LSB_OUT7
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT0
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT1
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT2
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT3
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT4
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT5
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT6
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,output [8 :0] ch0_xy_B_DEM_LSB_OUT7
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`endif
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`ifdef CHANNEL_Z_ON
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,output [14 :0] ch0_z_DEM_MSB_OUT0
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,output [14 :0] ch0_z_DEM_MSB_OUT1
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,output [14 :0] ch0_z_DEM_MSB_OUT2
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,output [14 :0] ch0_z_DEM_MSB_OUT3
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,output [6 :0] ch0_z_DEM_ISB_OUT0
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,output [6 :0] ch0_z_DEM_ISB_OUT1
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,output [6 :0] ch0_z_DEM_ISB_OUT2
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,output [6 :0] ch0_z_DEM_ISB_OUT3
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,output [8 :0] ch0_z_DEM_LSB_OUT0
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,output [8 :0] ch0_z_DEM_LSB_OUT1
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,output [8 :0] ch0_z_DEM_LSB_OUT2
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,output [8 :0] ch0_z_DEM_LSB_OUT3
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`endif
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`ifdef CHANNEL_IS_FOUR
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//------------------------------Ch1 DSP data out----------------------------------------------------
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`ifdef CHANNEL_XY_ON
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,output [14:0] ch1_xy_A_DEM_MSB_OUT0
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,output [14:0] ch1_xy_A_DEM_MSB_OUT1
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,output [14:0] ch1_xy_A_DEM_MSB_OUT2
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,output [14:0] ch1_xy_A_DEM_MSB_OUT3
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,output [14:0] ch1_xy_A_DEM_MSB_OUT4
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,output [14:0] ch1_xy_A_DEM_MSB_OUT5
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,output [14:0] ch1_xy_A_DEM_MSB_OUT6
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,output [14:0] ch1_xy_A_DEM_MSB_OUT7
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,output [14:0] ch1_xy_B_DEM_MSB_OUT0
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,output [14:0] ch1_xy_B_DEM_MSB_OUT1
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,output [14:0] ch1_xy_B_DEM_MSB_OUT2
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,output [14:0] ch1_xy_B_DEM_MSB_OUT3
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,output [14:0] ch1_xy_B_DEM_MSB_OUT4
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,output [14:0] ch1_xy_B_DEM_MSB_OUT5
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,output [14:0] ch1_xy_B_DEM_MSB_OUT6
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,output [14:0] ch1_xy_B_DEM_MSB_OUT7
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT0
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT1
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT2
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT3
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT4
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT5
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT6
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,output [6 :0] ch1_xy_A_DEM_ISB_OUT7
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT0
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT1
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT2
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT3
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT4
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT5
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT6
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,output [6 :0] ch1_xy_B_DEM_ISB_OUT7
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT0
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT1
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT2
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT3
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT4
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT5
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT6
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,output [8 :0] ch1_xy_A_DEM_LSB_OUT7
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT0
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT1
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT2
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT3
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT4
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT5
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT6
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,output [8 :0] ch1_xy_B_DEM_LSB_OUT7
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`endif
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`ifdef CHANNEL_Z_ON
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,output [14 :0] ch1_z_DEM_MSB_OUT0
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,output [14 :0] ch1_z_DEM_MSB_OUT1
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,output [14 :0] ch1_z_DEM_MSB_OUT2
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,output [14 :0] ch1_z_DEM_MSB_OUT3
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,output [6 :0] ch1_z_DEM_ISB_OUT0
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,output [6 :0] ch1_z_DEM_ISB_OUT1
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,output [6 :0] ch1_z_DEM_ISB_OUT2
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,output [6 :0] ch1_z_DEM_ISB_OUT3
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,output [8 :0] ch1_z_DEM_LSB_OUT0
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,output [8 :0] ch1_z_DEM_LSB_OUT1
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,output [8 :0] ch1_z_DEM_LSB_OUT2
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,output [8 :0] ch1_z_DEM_LSB_OUT3
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`endif
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//------------------------------Ch2 DSP data out----------------------------------------------------
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`ifdef CHANNEL_XY_ON
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,output [14:0] ch2_xy_A_DEM_MSB_OUT0
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,output [14:0] ch2_xy_A_DEM_MSB_OUT1
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,output [14:0] ch2_xy_A_DEM_MSB_OUT2
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,output [14:0] ch2_xy_A_DEM_MSB_OUT3
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,output [14:0] ch2_xy_A_DEM_MSB_OUT4
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,output [14:0] ch2_xy_A_DEM_MSB_OUT5
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,output [14:0] ch2_xy_A_DEM_MSB_OUT6
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,output [14:0] ch2_xy_A_DEM_MSB_OUT7
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,output [14:0] ch2_xy_B_DEM_MSB_OUT0
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,output [14:0] ch2_xy_B_DEM_MSB_OUT1
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,output [14:0] ch2_xy_B_DEM_MSB_OUT2
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,output [14:0] ch2_xy_B_DEM_MSB_OUT3
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,output [14:0] ch2_xy_B_DEM_MSB_OUT4
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,output [14:0] ch2_xy_B_DEM_MSB_OUT5
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,output [14:0] ch2_xy_B_DEM_MSB_OUT6
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,output [14:0] ch2_xy_B_DEM_MSB_OUT7
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT0
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT1
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT2
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT3
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT4
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT5
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT6
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,output [6 :0] ch2_xy_A_DEM_ISB_OUT7
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,output [6 :0] ch2_xy_B_DEM_ISB_OUT0
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,output [6 :0] ch2_xy_B_DEM_ISB_OUT1
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,output [6 :0] ch2_xy_B_DEM_ISB_OUT2
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,output [6 :0] ch2_xy_B_DEM_ISB_OUT3
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,output [6 :0] ch2_xy_B_DEM_ISB_OUT4
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,output [6 :0] ch2_xy_B_DEM_ISB_OUT5
|
|
,output [6 :0] ch2_xy_B_DEM_ISB_OUT6
|
|
,output [6 :0] ch2_xy_B_DEM_ISB_OUT7
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT0
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT1
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT2
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT3
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT4
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT5
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT6
|
|
,output [8 :0] ch2_xy_A_DEM_LSB_OUT7
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT0
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT1
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT2
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT3
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT4
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT5
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT6
|
|
,output [8 :0] ch2_xy_B_DEM_LSB_OUT7
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,output [14 :0] ch2_z_DEM_MSB_OUT0
|
|
,output [14 :0] ch2_z_DEM_MSB_OUT1
|
|
,output [14 :0] ch2_z_DEM_MSB_OUT2
|
|
,output [14 :0] ch2_z_DEM_MSB_OUT3
|
|
,output [6 :0] ch2_z_DEM_ISB_OUT0
|
|
,output [6 :0] ch2_z_DEM_ISB_OUT1
|
|
,output [6 :0] ch2_z_DEM_ISB_OUT2
|
|
,output [6 :0] ch2_z_DEM_ISB_OUT3
|
|
,output [8 :0] ch2_z_DEM_LSB_OUT0
|
|
,output [8 :0] ch2_z_DEM_LSB_OUT1
|
|
,output [8 :0] ch2_z_DEM_LSB_OUT2
|
|
,output [8 :0] ch2_z_DEM_LSB_OUT3
|
|
`endif
|
|
//------------------------------Ch3 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT0
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT1
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT2
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT3
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT4
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT5
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT6
|
|
,output [14:0] ch3_xy_A_DEM_MSB_OUT7
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT0
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT1
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT2
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT3
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT4
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT5
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT6
|
|
,output [14:0] ch3_xy_B_DEM_MSB_OUT7
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT0
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT1
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT2
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT3
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT4
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT5
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT6
|
|
,output [6 :0] ch3_xy_A_DEM_ISB_OUT7
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT0
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT1
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT2
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT3
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT4
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT5
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT6
|
|
,output [6 :0] ch3_xy_B_DEM_ISB_OUT7
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT0
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT1
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT2
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT3
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT4
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT5
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT6
|
|
,output [8 :0] ch3_xy_A_DEM_LSB_OUT7
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT0
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT1
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT2
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT3
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT4
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT5
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT6
|
|
,output [8 :0] ch3_xy_B_DEM_LSB_OUT7
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,output [14 :0] ch3_z_DEM_MSB_OUT0
|
|
,output [14 :0] ch3_z_DEM_MSB_OUT1
|
|
,output [14 :0] ch3_z_DEM_MSB_OUT2
|
|
,output [14 :0] ch3_z_DEM_MSB_OUT3
|
|
,output [6 :0] ch3_z_DEM_ISB_OUT0
|
|
,output [6 :0] ch3_z_DEM_ISB_OUT1
|
|
,output [6 :0] ch3_z_DEM_ISB_OUT2
|
|
,output [6 :0] ch3_z_DEM_ISB_OUT3
|
|
,output [8 :0] ch3_z_DEM_LSB_OUT0
|
|
,output [8 :0] ch3_z_DEM_LSB_OUT1
|
|
,output [8 :0] ch3_z_DEM_LSB_OUT2
|
|
,output [8 :0] ch3_z_DEM_LSB_OUT3
|
|
`endif
|
|
`endif
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
// PIN END //
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
);
|
|
|
|
//------------------------------iopad instantiation start--------------------------------------
|
|
// iopad
|
|
//---------------------------------------------------------------------------------------------
|
|
wire async_rstn ;
|
|
wire sync_in ;
|
|
wire sync_out ;
|
|
wire [1 :0] ch0_feedback ;
|
|
`ifdef CHANNEL_IS_FOUR
|
|
wire [1 :0] ch1_feedback ;
|
|
wire [1 :0] ch2_feedback ;
|
|
wire [1 :0] ch3_feedback ;
|
|
`endif
|
|
wire [4 :0] cfgid ;
|
|
wire sclk ;
|
|
wire csn ;
|
|
wire mosi ;
|
|
wire miso ;
|
|
wire oen ;
|
|
wire irq ;
|
|
|
|
iopad U_iopad (
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
// PAD Strat //
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
.PI_async_rstn ( PI_async_rstn )
|
|
,.PI_sync_in ( PI_sync_in )
|
|
,.PO_sync_out ( PO_sync_out )
|
|
,.PI_ch0_feedback ( PI_ch0_feedback )
|
|
`ifdef CHANNEL_IS_FOUR
|
|
,.PI_ch1_feedback ( PI_ch1_feedback )
|
|
,.PI_ch2_feedback ( PI_ch2_feedback )
|
|
,.PI_ch3_feedback ( PI_ch3_feedback )
|
|
`endif
|
|
,.PI_cfgid ( PI_cfgid )
|
|
,.PI_sclk ( PI_sclk )
|
|
,.PI_csn ( PI_csn )
|
|
,.PI_mosi ( PI_mosi )
|
|
,.PO_miso ( PO_miso )
|
|
,.PO_irq ( PO_irq )
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
// PAD End //
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
// Internal signal Start //
|
|
//+++++++++++++++++++++++++++++++++++++++++++++//
|
|
,.async_rstn ( async_rstn )
|
|
,.sync_in ( sync_in )
|
|
,.sync_out ( sync_out )
|
|
,.ch0_feedback ( ch0_feedback )
|
|
`ifdef CHANNEL_IS_FOUR
|
|
,.ch1_feedback ( ch1_feedback )
|
|
,.ch2_feedback ( ch2_feedback )
|
|
,.ch3_feedback ( ch3_feedback )
|
|
`endif
|
|
,.cfgid ( cfgid )
|
|
,.sclk ( sclk )
|
|
,.csn ( csn )
|
|
,.mosi ( mosi )
|
|
,.miso ( miso )
|
|
,.oen ( oen )
|
|
,.irq ( irq )
|
|
);
|
|
//------------------------------iopad instantiation end---------------------------------------
|
|
// iopad
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
//------------------------------digital_top instantiation start--------------------------------
|
|
// digital_top
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
wire ch0_dac_Prbs ;
|
|
wire [14 :0] ch0_dac_Set0 ;
|
|
wire [14 :0] ch0_dac_Set1 ;
|
|
wire [14 :0] ch0_dac_Set2 ;
|
|
wire [14 :0] ch0_dac_Set3 ;
|
|
wire [14 :0] ch0_dac_Set4 ;
|
|
wire [14 :0] ch0_dac_Set5 ;
|
|
wire [14 :0] ch0_dac_Set6 ;
|
|
wire [14 :0] ch0_dac_Set7 ;
|
|
wire [14 :0] ch0_dac_Set8 ;
|
|
wire [14 :0] ch0_dac_Set9 ;
|
|
wire [14 :0] ch0_dac_Set10 ;
|
|
wire [14 :0] ch0_dac_Set11 ;
|
|
wire [14 :0] ch0_dac_Set12 ;
|
|
wire [14 :0] ch0_dac_Set13 ;
|
|
wire [14 :0] ch0_dac_Set14 ;
|
|
wire [14 :0] ch0_dac_Set15 ;
|
|
|
|
`ifdef CHANNEL_IS_FOUR
|
|
wire ch1_dac_Prbs ;
|
|
wire [14 :0] ch1_dac_Set0 ;
|
|
wire [14 :0] ch1_dac_Set1 ;
|
|
wire [14 :0] ch1_dac_Set2 ;
|
|
wire [14 :0] ch1_dac_Set3 ;
|
|
wire [14 :0] ch1_dac_Set4 ;
|
|
wire [14 :0] ch1_dac_Set5 ;
|
|
wire [14 :0] ch1_dac_Set6 ;
|
|
wire [14 :0] ch1_dac_Set7 ;
|
|
wire [14 :0] ch1_dac_Set8 ;
|
|
wire [14 :0] ch1_dac_Set9 ;
|
|
wire [14 :0] ch1_dac_Set10 ;
|
|
wire [14 :0] ch1_dac_Set11 ;
|
|
wire [14 :0] ch1_dac_Set12 ;
|
|
wire [14 :0] ch1_dac_Set13 ;
|
|
wire [14 :0] ch1_dac_Set14 ;
|
|
wire [14 :0] ch1_dac_Set15 ;
|
|
|
|
wire ch2_dac_Prbs ;
|
|
wire [14 :0] ch2_dac_Set0 ;
|
|
wire [14 :0] ch2_dac_Set1 ;
|
|
wire [14 :0] ch2_dac_Set2 ;
|
|
wire [14 :0] ch2_dac_Set3 ;
|
|
wire [14 :0] ch2_dac_Set4 ;
|
|
wire [14 :0] ch2_dac_Set5 ;
|
|
wire [14 :0] ch2_dac_Set6 ;
|
|
wire [14 :0] ch2_dac_Set7 ;
|
|
wire [14 :0] ch2_dac_Set8 ;
|
|
wire [14 :0] ch2_dac_Set9 ;
|
|
wire [14 :0] ch2_dac_Set10 ;
|
|
wire [14 :0] ch2_dac_Set11 ;
|
|
wire [14 :0] ch2_dac_Set12 ;
|
|
wire [14 :0] ch2_dac_Set13 ;
|
|
wire [14 :0] ch2_dac_Set14 ;
|
|
wire [14 :0] ch2_dac_Set15 ;
|
|
|
|
wire ch3_dac_Prbs ;
|
|
wire [14 :0] ch3_dac_Set0 ;
|
|
wire [14 :0] ch3_dac_Set1 ;
|
|
wire [14 :0] ch3_dac_Set2 ;
|
|
wire [14 :0] ch3_dac_Set3 ;
|
|
wire [14 :0] ch3_dac_Set4 ;
|
|
wire [14 :0] ch3_dac_Set5 ;
|
|
wire [14 :0] ch3_dac_Set6 ;
|
|
wire [14 :0] ch3_dac_Set7 ;
|
|
wire [14 :0] ch3_dac_Set8 ;
|
|
wire [14 :0] ch3_dac_Set9 ;
|
|
wire [14 :0] ch3_dac_Set10 ;
|
|
wire [14 :0] ch3_dac_Set11 ;
|
|
wire [14 :0] ch3_dac_Set12 ;
|
|
wire [14 :0] ch3_dac_Set13 ;
|
|
wire [14 :0] ch3_dac_Set14 ;
|
|
wire [14 :0] ch3_dac_Set15 ;
|
|
`endif
|
|
|
|
`ifdef CHANNEL_XY_ON
|
|
wire [15 :0] ch0_xy_dsp_dout0 ;
|
|
wire [15 :0] ch0_xy_dsp_dout1 ;
|
|
wire [15 :0] ch0_xy_dsp_dout2 ;
|
|
wire [15 :0] ch0_xy_dsp_dout3 ;
|
|
wire [15 :0] ch0_xy_dsp_dout4 ;
|
|
wire [15 :0] ch0_xy_dsp_dout5 ;
|
|
wire [15 :0] ch0_xy_dsp_dout6 ;
|
|
wire [15 :0] ch0_xy_dsp_dout7 ;
|
|
wire [15 :0] ch0_xy_dsp_dout8 ;
|
|
wire [15 :0] ch0_xy_dsp_dout9 ;
|
|
wire [15 :0] ch0_xy_dsp_dout10 ;
|
|
wire [15 :0] ch0_xy_dsp_dout11 ;
|
|
wire [15 :0] ch0_xy_dsp_dout12 ;
|
|
wire [15 :0] ch0_xy_dsp_dout13 ;
|
|
wire [15 :0] ch0_xy_dsp_dout14 ;
|
|
wire [15 :0] ch0_xy_dsp_dout15 ;
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
wire [15 :0] ch0_z_dsp_dout0 ;
|
|
wire [15 :0] ch0_z_dsp_dout1 ;
|
|
wire [15 :0] ch0_z_dsp_dout2 ;
|
|
wire [15 :0] ch0_z_dsp_dout3 ;
|
|
`endif
|
|
|
|
`ifdef CHANNEL_IS_FOUR
|
|
`ifdef CHANNEL_XY_ON
|
|
wire [15 :0] ch1_xy_dsp_dout0 ;
|
|
wire [15 :0] ch1_xy_dsp_dout1 ;
|
|
wire [15 :0] ch1_xy_dsp_dout2 ;
|
|
wire [15 :0] ch1_xy_dsp_dout3 ;
|
|
wire [15 :0] ch1_xy_dsp_dout4 ;
|
|
wire [15 :0] ch1_xy_dsp_dout5 ;
|
|
wire [15 :0] ch1_xy_dsp_dout6 ;
|
|
wire [15 :0] ch1_xy_dsp_dout7 ;
|
|
wire [15 :0] ch1_xy_dsp_dout8 ;
|
|
wire [15 :0] ch1_xy_dsp_dout9 ;
|
|
wire [15 :0] ch1_xy_dsp_dout10 ;
|
|
wire [15 :0] ch1_xy_dsp_dout11 ;
|
|
wire [15 :0] ch1_xy_dsp_dout12 ;
|
|
wire [15 :0] ch1_xy_dsp_dout13 ;
|
|
wire [15 :0] ch1_xy_dsp_dout14 ;
|
|
wire [15 :0] ch1_xy_dsp_dout15 ;
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
wire [15 :0] ch1_z_dsp_dout0 ;
|
|
wire [15 :0] ch1_z_dsp_dout1 ;
|
|
wire [15 :0] ch1_z_dsp_dout2 ;
|
|
wire [15 :0] ch1_z_dsp_dout3 ;
|
|
`endif
|
|
|
|
`ifdef CHANNEL_XY_ON
|
|
wire [15 :0] ch2_xy_dsp_dout0 ;
|
|
wire [15 :0] ch2_xy_dsp_dout1 ;
|
|
wire [15 :0] ch2_xy_dsp_dout2 ;
|
|
wire [15 :0] ch2_xy_dsp_dout3 ;
|
|
wire [15 :0] ch2_xy_dsp_dout4 ;
|
|
wire [15 :0] ch2_xy_dsp_dout5 ;
|
|
wire [15 :0] ch2_xy_dsp_dout6 ;
|
|
wire [15 :0] ch2_xy_dsp_dout7 ;
|
|
wire [15 :0] ch2_xy_dsp_dout8 ;
|
|
wire [15 :0] ch2_xy_dsp_dout9 ;
|
|
wire [15 :0] ch2_xy_dsp_dout10 ;
|
|
wire [15 :0] ch2_xy_dsp_dout11 ;
|
|
wire [15 :0] ch2_xy_dsp_dout12 ;
|
|
wire [15 :0] ch2_xy_dsp_dout13 ;
|
|
wire [15 :0] ch2_xy_dsp_dout14 ;
|
|
wire [15 :0] ch2_xy_dsp_dout15 ;
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
wire [15 :0] ch2_z_dsp_dout0 ;
|
|
wire [15 :0] ch2_z_dsp_dout1 ;
|
|
wire [15 :0] ch2_z_dsp_dout2 ;
|
|
wire [15 :0] ch2_z_dsp_dout3 ;
|
|
`endif
|
|
|
|
`ifdef CHANNEL_XY_ON
|
|
wire [15 :0] ch3_xy_dsp_dout0 ;
|
|
wire [15 :0] ch3_xy_dsp_dout1 ;
|
|
wire [15 :0] ch3_xy_dsp_dout2 ;
|
|
wire [15 :0] ch3_xy_dsp_dout3 ;
|
|
wire [15 :0] ch3_xy_dsp_dout4 ;
|
|
wire [15 :0] ch3_xy_dsp_dout5 ;
|
|
wire [15 :0] ch3_xy_dsp_dout6 ;
|
|
wire [15 :0] ch3_xy_dsp_dout7 ;
|
|
wire [15 :0] ch3_xy_dsp_dout8 ;
|
|
wire [15 :0] ch3_xy_dsp_dout9 ;
|
|
wire [15 :0] ch3_xy_dsp_dout10 ;
|
|
wire [15 :0] ch3_xy_dsp_dout11 ;
|
|
wire [15 :0] ch3_xy_dsp_dout12 ;
|
|
wire [15 :0] ch3_xy_dsp_dout13 ;
|
|
wire [15 :0] ch3_xy_dsp_dout14 ;
|
|
wire [15 :0] ch3_xy_dsp_dout15 ;
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
wire [15 :0] ch3_z_dsp_dout0 ;
|
|
wire [15 :0] ch3_z_dsp_dout1 ;
|
|
wire [15 :0] ch3_z_dsp_dout2 ;
|
|
wire [15 :0] ch3_z_dsp_dout3 ;
|
|
`endif
|
|
`endif
|
|
|
|
digital_top U_digital_top (
|
|
.clk ( clk )
|
|
,.por_rstn ( por_rstn )
|
|
,.async_rstn ( async_rstn )
|
|
,.sync_in ( sync_in )
|
|
,.sync_out ( sync_out )
|
|
,.ch0_feedback ( ch0_feedback )
|
|
`ifdef CHANNEL_IS_FOUR
|
|
,.ch1_feedback ( ch1_feedback )
|
|
,.ch2_feedback ( ch2_feedback )
|
|
,.ch3_feedback ( ch3_feedback )
|
|
`endif
|
|
,.cfgid ( cfgid )
|
|
,.sclk ( sclk )
|
|
,.csn ( csn )
|
|
,.mosi ( mosi )
|
|
,.miso ( miso )
|
|
,.oen ( oen )
|
|
,.irq ( irq )
|
|
,.ref_sel ( ref_sel )
|
|
,.ref_en ( ref_en )
|
|
,.ref_s2d_en ( ref_s2d_en )
|
|
,.p_cnt ( p_cnt )
|
|
,.pfd_delay ( pfd_delay )
|
|
,.pfd_dff_Set ( pfd_dff_Set )
|
|
,.pfd_dff_4and ( pfd_dff_4and )
|
|
,.spd_div ( spd_div )
|
|
,.spd_pulse_width ( spd_pulse_width )
|
|
,.spd_pulse_sw ( spd_pulse_sw )
|
|
,.cpc_sel ( cpc_sel )
|
|
,.swcp_i ( swcp_i )
|
|
,.sw_ptat_r ( sw_ptat_r )
|
|
,.sw_fll_cpi ( sw_fll_cpi )
|
|
,.sw_fll_delay ( sw_fll_delay )
|
|
,.pfd_sel ( pfd_sel )
|
|
,.spd_sel ( spd_sel )
|
|
,.fll_sel ( fll_sel )
|
|
,.vco_tc ( vco_tc )
|
|
,.vco_tcr ( vco_tcr )
|
|
,.vco_gain_adj ( vco_gain_adj )
|
|
,.vco_gain_adj_r ( vco_gain_adj_r )
|
|
,.vco_cur_adj ( vco_cur_adj )
|
|
,.vco_buff_en ( vco_buff_en )
|
|
,.vco_en ( vco_en )
|
|
,.pll_dpwr_adj ( pll_dpwr_adj )
|
|
,.vco_fb_adj ( vco_fb_adj )
|
|
,.afc_en ( afc_en )
|
|
,.afc_shutdown ( afc_shutdown )
|
|
,.afc_det_speed ( afc_det_speed )
|
|
,.flag_out_sel ( flag_out_sel )
|
|
,.afc_reset ( afc_reset )
|
|
,.afc_cnt ( afc_cnt )
|
|
,.afc_ld_cnt ( afc_ld_cnt )
|
|
,.afc_pres ( afc_pres )
|
|
,.afc_ld_tcc ( afc_ld_tcc )
|
|
,.afc_fb_tcc ( afc_fb_tcc )
|
|
,.sync_clr ( sync_clr )
|
|
,.pll_rstn ( pll_rstn )
|
|
,.div_rstn_sel ( div_rstn_sel )
|
|
,.test_clk_sel ( test_clk_sel )
|
|
,.test_clk_oen ( test_clk_oen )
|
|
,.dig_clk_sel ( dig_clk_sel )
|
|
,.clkrx_pdn ( clkrx_pdn )
|
|
,.pll_lock ( pll_lock )
|
|
//------------------------------Ch0 DAC cfg pin----------------------------------------------------
|
|
,.ch0_dac_Prbs ( ch0_dac_Prbs )
|
|
,.ch0_dac_Set0 ( ch0_dac_Set0 )
|
|
,.ch0_dac_Set1 ( ch0_dac_Set1 )
|
|
,.ch0_dac_Set2 ( ch0_dac_Set2 )
|
|
,.ch0_dac_Set3 ( ch0_dac_Set3 )
|
|
,.ch0_dac_Set4 ( ch0_dac_Set4 )
|
|
,.ch0_dac_Set5 ( ch0_dac_Set5 )
|
|
,.ch0_dac_Set6 ( ch0_dac_Set6 )
|
|
,.ch0_dac_Set7 ( ch0_dac_Set7 )
|
|
,.ch0_dac_Set8 ( ch0_dac_Set8 )
|
|
,.ch0_dac_Set9 ( ch0_dac_Set9 )
|
|
,.ch0_dac_Set10 ( ch0_dac_Set10 )
|
|
,.ch0_dac_Set11 ( ch0_dac_Set11 )
|
|
,.ch0_dac_Set12 ( ch0_dac_Set12 )
|
|
,.ch0_dac_Set13 ( ch0_dac_Set13 )
|
|
,.ch0_dac_Set14 ( ch0_dac_Set14 )
|
|
,.ch0_dac_Set15 ( ch0_dac_Set15 )
|
|
,.ch0_dac_addr ( ch0_dac_addr )
|
|
,.ch0_dac_dw ( ch0_dac_dw )
|
|
,.ch0_dac_ref ( ch0_dac_ref )
|
|
,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 )
|
|
,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 )
|
|
,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 )
|
|
,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 )
|
|
,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig )
|
|
,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn )
|
|
,.ch0_dac_Cal_div_rstn ( ch0_dac_Cal_div_rstn )
|
|
,.ch0_dac_Cal_end ( ch0_dac_Cal_end )
|
|
`ifdef CHANNEL_IS_FOUR
|
|
//------------------------------Ch1 DAC cfg pin----------------------------------------------------
|
|
,.ch1_dac_Prbs ( ch1_dac_Prbs )
|
|
,.ch1_dac_Set0 ( ch1_dac_Set0 )
|
|
,.ch1_dac_Set1 ( ch1_dac_Set1 )
|
|
,.ch1_dac_Set2 ( ch1_dac_Set2 )
|
|
,.ch1_dac_Set3 ( ch1_dac_Set3 )
|
|
,.ch1_dac_Set4 ( ch1_dac_Set4 )
|
|
,.ch1_dac_Set5 ( ch1_dac_Set5 )
|
|
,.ch1_dac_Set6 ( ch1_dac_Set6 )
|
|
,.ch1_dac_Set7 ( ch1_dac_Set7 )
|
|
,.ch1_dac_Set8 ( ch1_dac_Set8 )
|
|
,.ch1_dac_Set9 ( ch1_dac_Set9 )
|
|
,.ch1_dac_Set10 ( ch1_dac_Set10 )
|
|
,.ch1_dac_Set11 ( ch1_dac_Set11 )
|
|
,.ch1_dac_Set12 ( ch1_dac_Set12 )
|
|
,.ch1_dac_Set13 ( ch1_dac_Set13 )
|
|
,.ch1_dac_Set14 ( ch1_dac_Set14 )
|
|
,.ch1_dac_Set15 ( ch1_dac_Set15 )
|
|
,.ch1_dac_addr ( ch1_dac_addr )
|
|
,.ch1_dac_dw ( ch1_dac_dw )
|
|
,.ch1_dac_ref ( ch1_dac_ref )
|
|
,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 )
|
|
,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 )
|
|
,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 )
|
|
,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 )
|
|
,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig )
|
|
,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn )
|
|
,.ch1_dac_Cal_div_rstn ( ch1_dac_Cal_div_rstn )
|
|
,.ch1_dac_Cal_end ( ch1_dac_Cal_end )
|
|
//------------------------------Ch2 DAC cfg pin----------------------------------------------------
|
|
,.ch2_dac_Prbs ( ch2_dac_Prbs )
|
|
,.ch2_dac_Set0 ( ch2_dac_Set0 )
|
|
,.ch2_dac_Set1 ( ch2_dac_Set1 )
|
|
,.ch2_dac_Set2 ( ch2_dac_Set2 )
|
|
,.ch2_dac_Set3 ( ch2_dac_Set3 )
|
|
,.ch2_dac_Set4 ( ch2_dac_Set4 )
|
|
,.ch2_dac_Set5 ( ch2_dac_Set5 )
|
|
,.ch2_dac_Set6 ( ch2_dac_Set6 )
|
|
,.ch2_dac_Set7 ( ch2_dac_Set7 )
|
|
,.ch2_dac_Set8 ( ch2_dac_Set8 )
|
|
,.ch2_dac_Set9 ( ch2_dac_Set9 )
|
|
,.ch2_dac_Set10 ( ch2_dac_Set10 )
|
|
,.ch2_dac_Set11 ( ch2_dac_Set11 )
|
|
,.ch2_dac_Set12 ( ch2_dac_Set12 )
|
|
,.ch2_dac_Set13 ( ch2_dac_Set13 )
|
|
,.ch2_dac_Set14 ( ch2_dac_Set14 )
|
|
,.ch2_dac_Set15 ( ch2_dac_Set15 )
|
|
,.ch2_dac_addr ( ch2_dac_addr )
|
|
,.ch2_dac_dw ( ch2_dac_dw )
|
|
,.ch2_dac_ref ( ch2_dac_ref )
|
|
,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 )
|
|
,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 )
|
|
,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 )
|
|
,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 )
|
|
,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig )
|
|
,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn )
|
|
,.ch2_dac_Cal_div_rstn ( ch2_dac_Cal_div_rstn )
|
|
,.ch2_dac_Cal_end ( ch2_dac_Cal_end )
|
|
//------------------------------Ch3 DAC cfg pin----------------------------------------------------
|
|
,.ch3_dac_Prbs ( ch3_dac_Prbs )
|
|
,.ch3_dac_Set0 ( ch3_dac_Set0 )
|
|
,.ch3_dac_Set1 ( ch3_dac_Set1 )
|
|
,.ch3_dac_Set2 ( ch3_dac_Set2 )
|
|
,.ch3_dac_Set3 ( ch3_dac_Set3 )
|
|
,.ch3_dac_Set4 ( ch3_dac_Set4 )
|
|
,.ch3_dac_Set5 ( ch3_dac_Set5 )
|
|
,.ch3_dac_Set6 ( ch3_dac_Set6 )
|
|
,.ch3_dac_Set7 ( ch3_dac_Set7 )
|
|
,.ch3_dac_Set8 ( ch3_dac_Set8 )
|
|
,.ch3_dac_Set9 ( ch3_dac_Set9 )
|
|
,.ch3_dac_Set10 ( ch3_dac_Set10 )
|
|
,.ch3_dac_Set11 ( ch3_dac_Set11 )
|
|
,.ch3_dac_Set12 ( ch3_dac_Set12 )
|
|
,.ch3_dac_Set13 ( ch3_dac_Set13 )
|
|
,.ch3_dac_Set14 ( ch3_dac_Set14 )
|
|
,.ch3_dac_Set15 ( ch3_dac_Set15 )
|
|
,.ch3_dac_addr ( ch3_dac_addr )
|
|
,.ch3_dac_dw ( ch3_dac_dw )
|
|
,.ch3_dac_ref ( ch3_dac_ref )
|
|
,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 )
|
|
,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 )
|
|
,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 )
|
|
,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 )
|
|
,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig )
|
|
,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn )
|
|
,.ch3_dac_Cal_div_rstn ( ch3_dac_Cal_div_rstn )
|
|
,.ch3_dac_Cal_end ( ch3_dac_Cal_end )
|
|
`endif
|
|
//------------------------------Ch0 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch0_xy_dsp_dout0 ( ch0_xy_dsp_dout0 )
|
|
,.ch0_xy_dsp_dout1 ( ch0_xy_dsp_dout1 )
|
|
,.ch0_xy_dsp_dout2 ( ch0_xy_dsp_dout2 )
|
|
,.ch0_xy_dsp_dout3 ( ch0_xy_dsp_dout3 )
|
|
,.ch0_xy_dsp_dout4 ( ch0_xy_dsp_dout4 )
|
|
,.ch0_xy_dsp_dout5 ( ch0_xy_dsp_dout5 )
|
|
,.ch0_xy_dsp_dout6 ( ch0_xy_dsp_dout6 )
|
|
,.ch0_xy_dsp_dout7 ( ch0_xy_dsp_dout7 )
|
|
,.ch0_xy_dsp_dout8 ( ch0_xy_dsp_dout8 )
|
|
,.ch0_xy_dsp_dout9 ( ch0_xy_dsp_dout9 )
|
|
,.ch0_xy_dsp_dout10 ( ch0_xy_dsp_dout10 )
|
|
,.ch0_xy_dsp_dout11 ( ch0_xy_dsp_dout11 )
|
|
,.ch0_xy_dsp_dout12 ( ch0_xy_dsp_dout12 )
|
|
,.ch0_xy_dsp_dout13 ( ch0_xy_dsp_dout13 )
|
|
,.ch0_xy_dsp_dout14 ( ch0_xy_dsp_dout14 )
|
|
,.ch0_xy_dsp_dout15 ( ch0_xy_dsp_dout15 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch0_z_dsp_dout0 ( ch0_z_dsp_dout0 )
|
|
,.ch0_z_dsp_dout1 ( ch0_z_dsp_dout1 )
|
|
,.ch0_z_dsp_dout2 ( ch0_z_dsp_dout2 )
|
|
,.ch0_z_dsp_dout3 ( ch0_z_dsp_dout3 )
|
|
`endif
|
|
`ifdef CHANNEL_IS_FOUR
|
|
//------------------------------Ch1 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch1_xy_dsp_dout0 ( ch1_xy_dsp_dout0 )
|
|
,.ch1_xy_dsp_dout1 ( ch1_xy_dsp_dout1 )
|
|
,.ch1_xy_dsp_dout2 ( ch1_xy_dsp_dout2 )
|
|
,.ch1_xy_dsp_dout3 ( ch1_xy_dsp_dout3 )
|
|
,.ch1_xy_dsp_dout4 ( ch1_xy_dsp_dout4 )
|
|
,.ch1_xy_dsp_dout5 ( ch1_xy_dsp_dout5 )
|
|
,.ch1_xy_dsp_dout6 ( ch1_xy_dsp_dout6 )
|
|
,.ch1_xy_dsp_dout7 ( ch1_xy_dsp_dout7 )
|
|
,.ch1_xy_dsp_dout8 ( ch1_xy_dsp_dout8 )
|
|
,.ch1_xy_dsp_dout9 ( ch1_xy_dsp_dout9 )
|
|
,.ch1_xy_dsp_dout10 ( ch1_xy_dsp_dout10 )
|
|
,.ch1_xy_dsp_dout11 ( ch1_xy_dsp_dout11 )
|
|
,.ch1_xy_dsp_dout12 ( ch1_xy_dsp_dout12 )
|
|
,.ch1_xy_dsp_dout13 ( ch1_xy_dsp_dout13 )
|
|
,.ch1_xy_dsp_dout14 ( ch1_xy_dsp_dout14 )
|
|
,.ch1_xy_dsp_dout15 ( ch1_xy_dsp_dout15 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch1_z_dsp_dout0 ( ch1_z_dsp_dout0 )
|
|
,.ch1_z_dsp_dout1 ( ch1_z_dsp_dout1 )
|
|
,.ch1_z_dsp_dout2 ( ch1_z_dsp_dout2 )
|
|
,.ch1_z_dsp_dout3 ( ch1_z_dsp_dout3 )
|
|
`endif
|
|
//------------------------------Ch2 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch2_xy_dsp_dout0 ( ch2_xy_dsp_dout0 )
|
|
,.ch2_xy_dsp_dout1 ( ch2_xy_dsp_dout1 )
|
|
,.ch2_xy_dsp_dout2 ( ch2_xy_dsp_dout2 )
|
|
,.ch2_xy_dsp_dout3 ( ch2_xy_dsp_dout3 )
|
|
,.ch2_xy_dsp_dout4 ( ch2_xy_dsp_dout4 )
|
|
,.ch2_xy_dsp_dout5 ( ch2_xy_dsp_dout5 )
|
|
,.ch2_xy_dsp_dout6 ( ch2_xy_dsp_dout6 )
|
|
,.ch2_xy_dsp_dout7 ( ch2_xy_dsp_dout7 )
|
|
,.ch2_xy_dsp_dout8 ( ch2_xy_dsp_dout8 )
|
|
,.ch2_xy_dsp_dout9 ( ch2_xy_dsp_dout9 )
|
|
,.ch2_xy_dsp_dout10 ( ch2_xy_dsp_dout10 )
|
|
,.ch2_xy_dsp_dout11 ( ch2_xy_dsp_dout11 )
|
|
,.ch2_xy_dsp_dout12 ( ch2_xy_dsp_dout12 )
|
|
,.ch2_xy_dsp_dout13 ( ch2_xy_dsp_dout13 )
|
|
,.ch2_xy_dsp_dout14 ( ch2_xy_dsp_dout14 )
|
|
,.ch2_xy_dsp_dout15 ( ch2_xy_dsp_dout15 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch2_z_dsp_dout0 ( ch2_z_dsp_dout0 )
|
|
,.ch2_z_dsp_dout1 ( ch2_z_dsp_dout1 )
|
|
,.ch2_z_dsp_dout2 ( ch2_z_dsp_dout2 )
|
|
,.ch2_z_dsp_dout3 ( ch2_z_dsp_dout3 )
|
|
`endif
|
|
//------------------------------Ch3 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch3_xy_dsp_dout0 ( ch3_xy_dsp_dout0 )
|
|
,.ch3_xy_dsp_dout1 ( ch3_xy_dsp_dout1 )
|
|
,.ch3_xy_dsp_dout2 ( ch3_xy_dsp_dout2 )
|
|
,.ch3_xy_dsp_dout3 ( ch3_xy_dsp_dout3 )
|
|
,.ch3_xy_dsp_dout4 ( ch3_xy_dsp_dout4 )
|
|
,.ch3_xy_dsp_dout5 ( ch3_xy_dsp_dout5 )
|
|
,.ch3_xy_dsp_dout6 ( ch3_xy_dsp_dout6 )
|
|
,.ch3_xy_dsp_dout7 ( ch3_xy_dsp_dout7 )
|
|
,.ch3_xy_dsp_dout8 ( ch3_xy_dsp_dout8 )
|
|
,.ch3_xy_dsp_dout9 ( ch3_xy_dsp_dout9 )
|
|
,.ch3_xy_dsp_dout10 ( ch3_xy_dsp_dout10 )
|
|
,.ch3_xy_dsp_dout11 ( ch3_xy_dsp_dout11 )
|
|
,.ch3_xy_dsp_dout12 ( ch3_xy_dsp_dout12 )
|
|
,.ch3_xy_dsp_dout13 ( ch3_xy_dsp_dout13 )
|
|
,.ch3_xy_dsp_dout14 ( ch3_xy_dsp_dout14 )
|
|
,.ch3_xy_dsp_dout15 ( ch3_xy_dsp_dout15 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch3_z_dsp_dout0 ( ch3_z_dsp_dout0 )
|
|
,.ch3_z_dsp_dout1 ( ch3_z_dsp_dout1 )
|
|
,.ch3_z_dsp_dout2 ( ch3_z_dsp_dout2 )
|
|
,.ch3_z_dsp_dout3 ( ch3_z_dsp_dout3 )
|
|
`endif
|
|
`endif
|
|
);
|
|
|
|
//------------------------------digital_top instantiation end----------------------------------
|
|
// digital_top
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
`ifdef CHANNEL_XY_ON
|
|
//------------------------------XY ch0 DAC_DEM_16 instantiation start--------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
DAC_DEM_16 U0_DAC_DEM_16 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch0_dac_Prbs )
|
|
,.set0 ( ch0_dac_Set0 )
|
|
,.set1 ( ch0_dac_Set1 )
|
|
,.set2 ( ch0_dac_Set2 )
|
|
,.set3 ( ch0_dac_Set3 )
|
|
,.set4 ( ch0_dac_Set4 )
|
|
,.set5 ( ch0_dac_Set5 )
|
|
,.set6 ( ch0_dac_Set6 )
|
|
,.set7 ( ch0_dac_Set7 )
|
|
,.set8 ( ch0_dac_Set8 )
|
|
,.set9 ( ch0_dac_Set9 )
|
|
,.set10 ( ch0_dac_Set10 )
|
|
,.set11 ( ch0_dac_Set11 )
|
|
,.set12 ( ch0_dac_Set12 )
|
|
,.set13 ( ch0_dac_Set13 )
|
|
,.set14 ( ch0_dac_Set14 )
|
|
,.set15 ( ch0_dac_Set15 )
|
|
|
|
,.DATA_IN0 ( ch0_xy_dsp_dout0 )
|
|
,.DATA_IN1 ( ch0_xy_dsp_dout1 )
|
|
,.DATA_IN2 ( ch0_xy_dsp_dout2 )
|
|
,.DATA_IN3 ( ch0_xy_dsp_dout3 )
|
|
,.DATA_IN4 ( ch0_xy_dsp_dout4 )
|
|
,.DATA_IN5 ( ch0_xy_dsp_dout5 )
|
|
,.DATA_IN6 ( ch0_xy_dsp_dout6 )
|
|
,.DATA_IN7 ( ch0_xy_dsp_dout7 )
|
|
,.DATA_IN8 ( ch0_xy_dsp_dout8 )
|
|
,.DATA_IN9 ( ch0_xy_dsp_dout9 )
|
|
,.DATA_IN10 ( ch0_xy_dsp_dout10 )
|
|
,.DATA_IN11 ( ch0_xy_dsp_dout11 )
|
|
,.DATA_IN12 ( ch0_xy_dsp_dout12 )
|
|
,.DATA_IN13 ( ch0_xy_dsp_dout13 )
|
|
,.DATA_IN14 ( ch0_xy_dsp_dout14 )
|
|
,.DATA_IN15 ( ch0_xy_dsp_dout15 )
|
|
|
|
,.A_DEM_MSB_OUT0 ( ch0_xy_A_DEM_MSB_OUT0 )
|
|
,.A_DEM_MSB_OUT1 ( ch0_xy_A_DEM_MSB_OUT1 )
|
|
,.A_DEM_MSB_OUT2 ( ch0_xy_A_DEM_MSB_OUT2 )
|
|
,.A_DEM_MSB_OUT3 ( ch0_xy_A_DEM_MSB_OUT3 )
|
|
,.A_DEM_MSB_OUT4 ( ch0_xy_A_DEM_MSB_OUT4 )
|
|
,.A_DEM_MSB_OUT5 ( ch0_xy_A_DEM_MSB_OUT5 )
|
|
,.A_DEM_MSB_OUT6 ( ch0_xy_A_DEM_MSB_OUT6 )
|
|
,.A_DEM_MSB_OUT7 ( ch0_xy_A_DEM_MSB_OUT7 )
|
|
|
|
,.A_DEM_ISB_OUT0 ( ch0_xy_A_DEM_ISB_OUT0 )
|
|
,.A_DEM_ISB_OUT1 ( ch0_xy_A_DEM_ISB_OUT1 )
|
|
,.A_DEM_ISB_OUT2 ( ch0_xy_A_DEM_ISB_OUT2 )
|
|
,.A_DEM_ISB_OUT3 ( ch0_xy_A_DEM_ISB_OUT3 )
|
|
,.A_DEM_ISB_OUT4 ( ch0_xy_A_DEM_ISB_OUT4 )
|
|
,.A_DEM_ISB_OUT5 ( ch0_xy_A_DEM_ISB_OUT5 )
|
|
,.A_DEM_ISB_OUT6 ( ch0_xy_A_DEM_ISB_OUT6 )
|
|
,.A_DEM_ISB_OUT7 ( ch0_xy_A_DEM_ISB_OUT7 )
|
|
|
|
,.A_DEM_LSB_OUT0 ( ch0_xy_A_DEM_LSB_OUT0 )
|
|
,.A_DEM_LSB_OUT1 ( ch0_xy_A_DEM_LSB_OUT1 )
|
|
,.A_DEM_LSB_OUT2 ( ch0_xy_A_DEM_LSB_OUT2 )
|
|
,.A_DEM_LSB_OUT3 ( ch0_xy_A_DEM_LSB_OUT3 )
|
|
,.A_DEM_LSB_OUT4 ( ch0_xy_A_DEM_LSB_OUT4 )
|
|
,.A_DEM_LSB_OUT5 ( ch0_xy_A_DEM_LSB_OUT5 )
|
|
,.A_DEM_LSB_OUT6 ( ch0_xy_A_DEM_LSB_OUT6 )
|
|
,.A_DEM_LSB_OUT7 ( ch0_xy_A_DEM_LSB_OUT7 )
|
|
|
|
,.B_DEM_MSB_OUT0 ( ch0_xy_B_DEM_MSB_OUT0 )
|
|
,.B_DEM_MSB_OUT1 ( ch0_xy_B_DEM_MSB_OUT1 )
|
|
,.B_DEM_MSB_OUT2 ( ch0_xy_B_DEM_MSB_OUT2 )
|
|
,.B_DEM_MSB_OUT3 ( ch0_xy_B_DEM_MSB_OUT3 )
|
|
,.B_DEM_MSB_OUT4 ( ch0_xy_B_DEM_MSB_OUT4 )
|
|
,.B_DEM_MSB_OUT5 ( ch0_xy_B_DEM_MSB_OUT5 )
|
|
,.B_DEM_MSB_OUT6 ( ch0_xy_B_DEM_MSB_OUT6 )
|
|
,.B_DEM_MSB_OUT7 ( ch0_xy_B_DEM_MSB_OUT7 )
|
|
|
|
,.B_DEM_ISB_OUT0 ( ch0_xy_B_DEM_ISB_OUT0 )
|
|
,.B_DEM_ISB_OUT1 ( ch0_xy_B_DEM_ISB_OUT1 )
|
|
,.B_DEM_ISB_OUT2 ( ch0_xy_B_DEM_ISB_OUT2 )
|
|
,.B_DEM_ISB_OUT3 ( ch0_xy_B_DEM_ISB_OUT3 )
|
|
,.B_DEM_ISB_OUT4 ( ch0_xy_B_DEM_ISB_OUT4 )
|
|
,.B_DEM_ISB_OUT5 ( ch0_xy_B_DEM_ISB_OUT5 )
|
|
,.B_DEM_ISB_OUT6 ( ch0_xy_B_DEM_ISB_OUT6 )
|
|
,.B_DEM_ISB_OUT7 ( ch0_xy_B_DEM_ISB_OUT7 )
|
|
|
|
,.B_DEM_LSB_OUT0 ( ch0_xy_B_DEM_LSB_OUT0 )
|
|
,.B_DEM_LSB_OUT1 ( ch0_xy_B_DEM_LSB_OUT1 )
|
|
,.B_DEM_LSB_OUT2 ( ch0_xy_B_DEM_LSB_OUT2 )
|
|
,.B_DEM_LSB_OUT3 ( ch0_xy_B_DEM_LSB_OUT3 )
|
|
,.B_DEM_LSB_OUT4 ( ch0_xy_B_DEM_LSB_OUT4 )
|
|
,.B_DEM_LSB_OUT5 ( ch0_xy_B_DEM_LSB_OUT5 )
|
|
,.B_DEM_LSB_OUT6 ( ch0_xy_B_DEM_LSB_OUT6 )
|
|
,.B_DEM_LSB_OUT7 ( ch0_xy_B_DEM_LSB_OUT7 )
|
|
);
|
|
`endif
|
|
//------------------------------XY ch0 DAC_DEM_16 instantiation end----------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
//------------------------------Z ch0 DAC_DEM_16 instantiation start---------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`ifdef CHANNEL_Z_ON
|
|
DAC_DEM_4 U0_DAC_DEM_4 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch0_dac_Prbs )
|
|
,.set0 ( ch0_dac_Set0 )
|
|
,.set1 ( ch0_dac_Set1 )
|
|
,.set2 ( ch0_dac_Set2 )
|
|
,.set3 ( ch0_dac_Set3 )
|
|
,.DATA_IN0 ( ch0_z_dsp_dout0 )
|
|
,.DATA_IN1 ( ch0_z_dsp_dout1 )
|
|
,.DATA_IN2 ( ch0_z_dsp_dout2 )
|
|
,.DATA_IN3 ( ch0_z_dsp_dout3 )
|
|
,.DEM_MSB_OUT0 ( ch0_z_DEM_MSB_OUT0 )
|
|
,.DEM_MSB_OUT1 ( ch0_z_DEM_MSB_OUT1 )
|
|
,.DEM_MSB_OUT2 ( ch0_z_DEM_MSB_OUT2 )
|
|
,.DEM_MSB_OUT3 ( ch0_z_DEM_MSB_OUT3 )
|
|
,.DEM_ISB_OUT0 ( ch0_z_DEM_ISB_OUT0 )
|
|
,.DEM_ISB_OUT1 ( ch0_z_DEM_ISB_OUT1 )
|
|
,.DEM_ISB_OUT2 ( ch0_z_DEM_ISB_OUT2 )
|
|
,.DEM_ISB_OUT3 ( ch0_z_DEM_ISB_OUT3 )
|
|
,.DEM_LSB_OUT0 ( ch0_z_DEM_LSB_OUT0 )
|
|
,.DEM_LSB_OUT1 ( ch0_z_DEM_LSB_OUT1 )
|
|
,.DEM_LSB_OUT2 ( ch0_z_DEM_LSB_OUT2 )
|
|
,.DEM_LSB_OUT3 ( ch0_z_DEM_LSB_OUT3 )
|
|
);
|
|
`endif
|
|
//------------------------------Z ch0 DAC_DEM instantiation end-----------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`ifdef CHANNEL_IS_FOUR
|
|
`ifdef CHANNEL_XY_ON
|
|
//------------------------------XY ch1 DAC_DEM_16 instantiation start--------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
DAC_DEM_16 U1_DAC_DEM_16 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch1_dac_Prbs )
|
|
,.set0 ( ch1_dac_Set0 )
|
|
,.set1 ( ch1_dac_Set1 )
|
|
,.set2 ( ch1_dac_Set2 )
|
|
,.set3 ( ch1_dac_Set3 )
|
|
,.set4 ( ch1_dac_Set4 )
|
|
,.set5 ( ch1_dac_Set5 )
|
|
,.set6 ( ch1_dac_Set6 )
|
|
,.set7 ( ch1_dac_Set7 )
|
|
,.set8 ( ch1_dac_Set8 )
|
|
,.set9 ( ch1_dac_Set9 )
|
|
,.set10 ( ch1_dac_Set10 )
|
|
,.set11 ( ch1_dac_Set11 )
|
|
,.set12 ( ch1_dac_Set12 )
|
|
,.set13 ( ch1_dac_Set13 )
|
|
,.set14 ( ch1_dac_Set14 )
|
|
,.set15 ( ch1_dac_Set15 )
|
|
|
|
,.DATA_IN0 ( ch1_xy_dsp_dout0 )
|
|
,.DATA_IN1 ( ch1_xy_dsp_dout1 )
|
|
,.DATA_IN2 ( ch1_xy_dsp_dout2 )
|
|
,.DATA_IN3 ( ch1_xy_dsp_dout3 )
|
|
,.DATA_IN4 ( ch1_xy_dsp_dout4 )
|
|
,.DATA_IN5 ( ch1_xy_dsp_dout5 )
|
|
,.DATA_IN6 ( ch1_xy_dsp_dout6 )
|
|
,.DATA_IN7 ( ch1_xy_dsp_dout7 )
|
|
,.DATA_IN8 ( ch1_xy_dsp_dout8 )
|
|
,.DATA_IN9 ( ch1_xy_dsp_dout9 )
|
|
,.DATA_IN10 ( ch1_xy_dsp_dout10 )
|
|
,.DATA_IN11 ( ch1_xy_dsp_dout11 )
|
|
,.DATA_IN12 ( ch1_xy_dsp_dout12 )
|
|
,.DATA_IN13 ( ch1_xy_dsp_dout13 )
|
|
,.DATA_IN14 ( ch1_xy_dsp_dout14 )
|
|
,.DATA_IN15 ( ch1_xy_dsp_dout15 )
|
|
|
|
,.A_DEM_MSB_OUT0 ( ch1_xy_A_DEM_MSB_OUT0 )
|
|
,.A_DEM_MSB_OUT1 ( ch1_xy_A_DEM_MSB_OUT1 )
|
|
,.A_DEM_MSB_OUT2 ( ch1_xy_A_DEM_MSB_OUT2 )
|
|
,.A_DEM_MSB_OUT3 ( ch1_xy_A_DEM_MSB_OUT3 )
|
|
,.A_DEM_MSB_OUT4 ( ch1_xy_A_DEM_MSB_OUT4 )
|
|
,.A_DEM_MSB_OUT5 ( ch1_xy_A_DEM_MSB_OUT5 )
|
|
,.A_DEM_MSB_OUT6 ( ch1_xy_A_DEM_MSB_OUT6 )
|
|
,.A_DEM_MSB_OUT7 ( ch1_xy_A_DEM_MSB_OUT7 )
|
|
|
|
,.A_DEM_ISB_OUT0 ( ch1_xy_A_DEM_ISB_OUT0 )
|
|
,.A_DEM_ISB_OUT1 ( ch1_xy_A_DEM_ISB_OUT1 )
|
|
,.A_DEM_ISB_OUT2 ( ch1_xy_A_DEM_ISB_OUT2 )
|
|
,.A_DEM_ISB_OUT3 ( ch1_xy_A_DEM_ISB_OUT3 )
|
|
,.A_DEM_ISB_OUT4 ( ch1_xy_A_DEM_ISB_OUT4 )
|
|
,.A_DEM_ISB_OUT5 ( ch1_xy_A_DEM_ISB_OUT5 )
|
|
,.A_DEM_ISB_OUT6 ( ch1_xy_A_DEM_ISB_OUT6 )
|
|
,.A_DEM_ISB_OUT7 ( ch1_xy_A_DEM_ISB_OUT7 )
|
|
|
|
,.A_DEM_LSB_OUT0 ( ch1_xy_A_DEM_LSB_OUT0 )
|
|
,.A_DEM_LSB_OUT1 ( ch1_xy_A_DEM_LSB_OUT1 )
|
|
,.A_DEM_LSB_OUT2 ( ch1_xy_A_DEM_LSB_OUT2 )
|
|
,.A_DEM_LSB_OUT3 ( ch1_xy_A_DEM_LSB_OUT3 )
|
|
,.A_DEM_LSB_OUT4 ( ch1_xy_A_DEM_LSB_OUT4 )
|
|
,.A_DEM_LSB_OUT5 ( ch1_xy_A_DEM_LSB_OUT5 )
|
|
,.A_DEM_LSB_OUT6 ( ch1_xy_A_DEM_LSB_OUT6 )
|
|
,.A_DEM_LSB_OUT7 ( ch1_xy_A_DEM_LSB_OUT7 )
|
|
|
|
,.B_DEM_MSB_OUT0 ( ch1_xy_B_DEM_MSB_OUT0 )
|
|
,.B_DEM_MSB_OUT1 ( ch1_xy_B_DEM_MSB_OUT1 )
|
|
,.B_DEM_MSB_OUT2 ( ch1_xy_B_DEM_MSB_OUT2 )
|
|
,.B_DEM_MSB_OUT3 ( ch1_xy_B_DEM_MSB_OUT3 )
|
|
,.B_DEM_MSB_OUT4 ( ch1_xy_B_DEM_MSB_OUT4 )
|
|
,.B_DEM_MSB_OUT5 ( ch1_xy_B_DEM_MSB_OUT5 )
|
|
,.B_DEM_MSB_OUT6 ( ch1_xy_B_DEM_MSB_OUT6 )
|
|
,.B_DEM_MSB_OUT7 ( ch1_xy_B_DEM_MSB_OUT7 )
|
|
|
|
,.B_DEM_ISB_OUT0 ( ch1_xy_B_DEM_ISB_OUT0 )
|
|
,.B_DEM_ISB_OUT1 ( ch1_xy_B_DEM_ISB_OUT1 )
|
|
,.B_DEM_ISB_OUT2 ( ch1_xy_B_DEM_ISB_OUT2 )
|
|
,.B_DEM_ISB_OUT3 ( ch1_xy_B_DEM_ISB_OUT3 )
|
|
,.B_DEM_ISB_OUT4 ( ch1_xy_B_DEM_ISB_OUT4 )
|
|
,.B_DEM_ISB_OUT5 ( ch1_xy_B_DEM_ISB_OUT5 )
|
|
,.B_DEM_ISB_OUT6 ( ch1_xy_B_DEM_ISB_OUT6 )
|
|
,.B_DEM_ISB_OUT7 ( ch1_xy_B_DEM_ISB_OUT7 )
|
|
|
|
,.B_DEM_LSB_OUT0 ( ch1_xy_B_DEM_LSB_OUT0 )
|
|
,.B_DEM_LSB_OUT1 ( ch1_xy_B_DEM_LSB_OUT1 )
|
|
,.B_DEM_LSB_OUT2 ( ch1_xy_B_DEM_LSB_OUT2 )
|
|
,.B_DEM_LSB_OUT3 ( ch1_xy_B_DEM_LSB_OUT3 )
|
|
,.B_DEM_LSB_OUT4 ( ch1_xy_B_DEM_LSB_OUT4 )
|
|
,.B_DEM_LSB_OUT5 ( ch1_xy_B_DEM_LSB_OUT5 )
|
|
,.B_DEM_LSB_OUT6 ( ch1_xy_B_DEM_LSB_OUT6 )
|
|
,.B_DEM_LSB_OUT7 ( ch1_xy_B_DEM_LSB_OUT7 )
|
|
);
|
|
`endif
|
|
//------------------------------XY ch1 DAC_DEM_16 instantiation end----------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
//------------------------------Z ch1 DAC_DEM_16 instantiation start---------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`ifdef CHANNEL_Z_ON
|
|
DAC_DEM_4 U1_DAC_DEM_4 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch1_dac_Prbs )
|
|
,.set0 ( ch1_dac_Set0 )
|
|
,.set1 ( ch1_dac_Set1 )
|
|
,.set2 ( ch1_dac_Set2 )
|
|
,.set3 ( ch1_dac_Set3 )
|
|
,.DATA_IN0 ( ch1_z_dsp_dout0 )
|
|
,.DATA_IN1 ( ch1_z_dsp_dout1 )
|
|
,.DATA_IN2 ( ch1_z_dsp_dout2 )
|
|
,.DATA_IN3 ( ch1_z_dsp_dout3 )
|
|
,.DEM_MSB_OUT0 ( ch1_z_DEM_MSB_OUT0 )
|
|
,.DEM_MSB_OUT1 ( ch1_z_DEM_MSB_OUT1 )
|
|
,.DEM_MSB_OUT2 ( ch1_z_DEM_MSB_OUT2 )
|
|
,.DEM_MSB_OUT3 ( ch1_z_DEM_MSB_OUT3 )
|
|
,.DEM_ISB_OUT0 ( ch1_z_DEM_ISB_OUT0 )
|
|
,.DEM_ISB_OUT1 ( ch1_z_DEM_ISB_OUT1 )
|
|
,.DEM_ISB_OUT2 ( ch1_z_DEM_ISB_OUT2 )
|
|
,.DEM_ISB_OUT3 ( ch1_z_DEM_ISB_OUT3 )
|
|
,.DEM_LSB_OUT0 ( ch1_z_DEM_LSB_OUT0 )
|
|
,.DEM_LSB_OUT1 ( ch1_z_DEM_LSB_OUT1 )
|
|
,.DEM_LSB_OUT2 ( ch1_z_DEM_LSB_OUT2 )
|
|
,.DEM_LSB_OUT3 ( ch1_z_DEM_LSB_OUT3 )
|
|
);
|
|
`endif
|
|
//------------------------------Z ch1 DAC_DEM instantiation end-----------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`ifdef CHANNEL_XY_ON
|
|
//------------------------------XY ch2 DAC_DEM_16 instantiation start--------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
DAC_DEM_16 U2_DAC_DEM_16 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch2_dac_Prbs )
|
|
,.set0 ( ch2_dac_Set0 )
|
|
,.set1 ( ch2_dac_Set1 )
|
|
,.set2 ( ch2_dac_Set2 )
|
|
,.set3 ( ch2_dac_Set3 )
|
|
,.set4 ( ch2_dac_Set4 )
|
|
,.set5 ( ch2_dac_Set5 )
|
|
,.set6 ( ch2_dac_Set6 )
|
|
,.set7 ( ch2_dac_Set7 )
|
|
,.set8 ( ch2_dac_Set8 )
|
|
,.set9 ( ch2_dac_Set9 )
|
|
,.set10 ( ch2_dac_Set10 )
|
|
,.set11 ( ch2_dac_Set11 )
|
|
,.set12 ( ch2_dac_Set12 )
|
|
,.set13 ( ch2_dac_Set13 )
|
|
,.set14 ( ch2_dac_Set14 )
|
|
,.set15 ( ch2_dac_Set15 )
|
|
|
|
,.DATA_IN0 ( ch2_xy_dsp_dout0 )
|
|
,.DATA_IN1 ( ch2_xy_dsp_dout1 )
|
|
,.DATA_IN2 ( ch2_xy_dsp_dout2 )
|
|
,.DATA_IN3 ( ch2_xy_dsp_dout3 )
|
|
,.DATA_IN4 ( ch2_xy_dsp_dout4 )
|
|
,.DATA_IN5 ( ch2_xy_dsp_dout5 )
|
|
,.DATA_IN6 ( ch2_xy_dsp_dout6 )
|
|
,.DATA_IN7 ( ch2_xy_dsp_dout7 )
|
|
,.DATA_IN8 ( ch2_xy_dsp_dout8 )
|
|
,.DATA_IN9 ( ch2_xy_dsp_dout9 )
|
|
,.DATA_IN10 ( ch2_xy_dsp_dout10 )
|
|
,.DATA_IN11 ( ch2_xy_dsp_dout11 )
|
|
,.DATA_IN12 ( ch2_xy_dsp_dout12 )
|
|
,.DATA_IN13 ( ch2_xy_dsp_dout13 )
|
|
,.DATA_IN14 ( ch2_xy_dsp_dout14 )
|
|
,.DATA_IN15 ( ch2_xy_dsp_dout15 )
|
|
|
|
,.A_DEM_MSB_OUT0 ( ch2_xy_A_DEM_MSB_OUT0 )
|
|
,.A_DEM_MSB_OUT1 ( ch2_xy_A_DEM_MSB_OUT1 )
|
|
,.A_DEM_MSB_OUT2 ( ch2_xy_A_DEM_MSB_OUT2 )
|
|
,.A_DEM_MSB_OUT3 ( ch2_xy_A_DEM_MSB_OUT3 )
|
|
,.A_DEM_MSB_OUT4 ( ch2_xy_A_DEM_MSB_OUT4 )
|
|
,.A_DEM_MSB_OUT5 ( ch2_xy_A_DEM_MSB_OUT5 )
|
|
,.A_DEM_MSB_OUT6 ( ch2_xy_A_DEM_MSB_OUT6 )
|
|
,.A_DEM_MSB_OUT7 ( ch2_xy_A_DEM_MSB_OUT7 )
|
|
|
|
,.A_DEM_ISB_OUT0 ( ch2_xy_A_DEM_ISB_OUT0 )
|
|
,.A_DEM_ISB_OUT1 ( ch2_xy_A_DEM_ISB_OUT1 )
|
|
,.A_DEM_ISB_OUT2 ( ch2_xy_A_DEM_ISB_OUT2 )
|
|
,.A_DEM_ISB_OUT3 ( ch2_xy_A_DEM_ISB_OUT3 )
|
|
,.A_DEM_ISB_OUT4 ( ch2_xy_A_DEM_ISB_OUT4 )
|
|
,.A_DEM_ISB_OUT5 ( ch2_xy_A_DEM_ISB_OUT5 )
|
|
,.A_DEM_ISB_OUT6 ( ch2_xy_A_DEM_ISB_OUT6 )
|
|
,.A_DEM_ISB_OUT7 ( ch2_xy_A_DEM_ISB_OUT7 )
|
|
|
|
,.A_DEM_LSB_OUT0 ( ch2_xy_A_DEM_LSB_OUT0 )
|
|
,.A_DEM_LSB_OUT1 ( ch2_xy_A_DEM_LSB_OUT1 )
|
|
,.A_DEM_LSB_OUT2 ( ch2_xy_A_DEM_LSB_OUT2 )
|
|
,.A_DEM_LSB_OUT3 ( ch2_xy_A_DEM_LSB_OUT3 )
|
|
,.A_DEM_LSB_OUT4 ( ch2_xy_A_DEM_LSB_OUT4 )
|
|
,.A_DEM_LSB_OUT5 ( ch2_xy_A_DEM_LSB_OUT5 )
|
|
,.A_DEM_LSB_OUT6 ( ch2_xy_A_DEM_LSB_OUT6 )
|
|
,.A_DEM_LSB_OUT7 ( ch2_xy_A_DEM_LSB_OUT7 )
|
|
|
|
,.B_DEM_MSB_OUT0 ( ch2_xy_B_DEM_MSB_OUT0 )
|
|
,.B_DEM_MSB_OUT1 ( ch2_xy_B_DEM_MSB_OUT1 )
|
|
,.B_DEM_MSB_OUT2 ( ch2_xy_B_DEM_MSB_OUT2 )
|
|
,.B_DEM_MSB_OUT3 ( ch2_xy_B_DEM_MSB_OUT3 )
|
|
,.B_DEM_MSB_OUT4 ( ch2_xy_B_DEM_MSB_OUT4 )
|
|
,.B_DEM_MSB_OUT5 ( ch2_xy_B_DEM_MSB_OUT5 )
|
|
,.B_DEM_MSB_OUT6 ( ch2_xy_B_DEM_MSB_OUT6 )
|
|
,.B_DEM_MSB_OUT7 ( ch2_xy_B_DEM_MSB_OUT7 )
|
|
|
|
,.B_DEM_ISB_OUT0 ( ch2_xy_B_DEM_ISB_OUT0 )
|
|
,.B_DEM_ISB_OUT1 ( ch2_xy_B_DEM_ISB_OUT1 )
|
|
,.B_DEM_ISB_OUT2 ( ch2_xy_B_DEM_ISB_OUT2 )
|
|
,.B_DEM_ISB_OUT3 ( ch2_xy_B_DEM_ISB_OUT3 )
|
|
,.B_DEM_ISB_OUT4 ( ch2_xy_B_DEM_ISB_OUT4 )
|
|
,.B_DEM_ISB_OUT5 ( ch2_xy_B_DEM_ISB_OUT5 )
|
|
,.B_DEM_ISB_OUT6 ( ch2_xy_B_DEM_ISB_OUT6 )
|
|
,.B_DEM_ISB_OUT7 ( ch2_xy_B_DEM_ISB_OUT7 )
|
|
|
|
,.B_DEM_LSB_OUT0 ( ch2_xy_B_DEM_LSB_OUT0 )
|
|
,.B_DEM_LSB_OUT1 ( ch2_xy_B_DEM_LSB_OUT1 )
|
|
,.B_DEM_LSB_OUT2 ( ch2_xy_B_DEM_LSB_OUT2 )
|
|
,.B_DEM_LSB_OUT3 ( ch2_xy_B_DEM_LSB_OUT3 )
|
|
,.B_DEM_LSB_OUT4 ( ch2_xy_B_DEM_LSB_OUT4 )
|
|
,.B_DEM_LSB_OUT5 ( ch2_xy_B_DEM_LSB_OUT5 )
|
|
,.B_DEM_LSB_OUT6 ( ch2_xy_B_DEM_LSB_OUT6 )
|
|
,.B_DEM_LSB_OUT7 ( ch2_xy_B_DEM_LSB_OUT7 )
|
|
);
|
|
`endif
|
|
//------------------------------XY ch2 DAC_DEM_16 instantiation end----------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
//------------------------------Z ch2 DAC_DEM_16 instantiation start---------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`ifdef CHANNEL_Z_ON
|
|
DAC_DEM_4 U2_DAC_DEM_4 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch2_dac_Prbs )
|
|
,.set0 ( ch2_dac_Set0 )
|
|
,.set1 ( ch2_dac_Set1 )
|
|
,.set2 ( ch2_dac_Set2 )
|
|
,.set3 ( ch2_dac_Set3 )
|
|
,.DATA_IN0 ( ch2_z_dsp_dout0 )
|
|
,.DATA_IN1 ( ch2_z_dsp_dout1 )
|
|
,.DATA_IN2 ( ch2_z_dsp_dout2 )
|
|
,.DATA_IN3 ( ch2_z_dsp_dout3 )
|
|
,.DEM_MSB_OUT0 ( ch2_z_DEM_MSB_OUT0 )
|
|
,.DEM_MSB_OUT1 ( ch2_z_DEM_MSB_OUT1 )
|
|
,.DEM_MSB_OUT2 ( ch2_z_DEM_MSB_OUT2 )
|
|
,.DEM_MSB_OUT3 ( ch2_z_DEM_MSB_OUT3 )
|
|
,.DEM_ISB_OUT0 ( ch2_z_DEM_ISB_OUT0 )
|
|
,.DEM_ISB_OUT1 ( ch2_z_DEM_ISB_OUT1 )
|
|
,.DEM_ISB_OUT2 ( ch2_z_DEM_ISB_OUT2 )
|
|
,.DEM_ISB_OUT3 ( ch2_z_DEM_ISB_OUT3 )
|
|
,.DEM_LSB_OUT0 ( ch2_z_DEM_LSB_OUT0 )
|
|
,.DEM_LSB_OUT1 ( ch2_z_DEM_LSB_OUT1 )
|
|
,.DEM_LSB_OUT2 ( ch2_z_DEM_LSB_OUT2 )
|
|
,.DEM_LSB_OUT3 ( ch2_z_DEM_LSB_OUT3 )
|
|
);
|
|
`endif
|
|
//------------------------------Z ch2 DAC_DEM instantiation end-----------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`ifdef CHANNEL_XY_ON
|
|
//------------------------------XY ch3 DAC_DEM_16 instantiation start--------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
DAC_DEM_16 U3_DAC_DEM_16 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch3_dac_Prbs )
|
|
,.set0 ( ch3_dac_Set0 )
|
|
,.set1 ( ch3_dac_Set1 )
|
|
,.set2 ( ch3_dac_Set2 )
|
|
,.set3 ( ch3_dac_Set3 )
|
|
,.set4 ( ch3_dac_Set4 )
|
|
,.set5 ( ch3_dac_Set5 )
|
|
,.set6 ( ch3_dac_Set6 )
|
|
,.set7 ( ch3_dac_Set7 )
|
|
,.set8 ( ch3_dac_Set8 )
|
|
,.set9 ( ch3_dac_Set9 )
|
|
,.set10 ( ch3_dac_Set10 )
|
|
,.set11 ( ch3_dac_Set11 )
|
|
,.set12 ( ch3_dac_Set12 )
|
|
,.set13 ( ch3_dac_Set13 )
|
|
,.set14 ( ch3_dac_Set14 )
|
|
,.set15 ( ch3_dac_Set15 )
|
|
|
|
,.DATA_IN0 ( ch3_xy_dsp_dout0 )
|
|
,.DATA_IN1 ( ch3_xy_dsp_dout1 )
|
|
,.DATA_IN2 ( ch3_xy_dsp_dout2 )
|
|
,.DATA_IN3 ( ch3_xy_dsp_dout3 )
|
|
,.DATA_IN4 ( ch3_xy_dsp_dout4 )
|
|
,.DATA_IN5 ( ch3_xy_dsp_dout5 )
|
|
,.DATA_IN6 ( ch3_xy_dsp_dout6 )
|
|
,.DATA_IN7 ( ch3_xy_dsp_dout7 )
|
|
,.DATA_IN8 ( ch3_xy_dsp_dout8 )
|
|
,.DATA_IN9 ( ch3_xy_dsp_dout9 )
|
|
,.DATA_IN10 ( ch3_xy_dsp_dout10 )
|
|
,.DATA_IN11 ( ch3_xy_dsp_dout11 )
|
|
,.DATA_IN12 ( ch3_xy_dsp_dout12 )
|
|
,.DATA_IN13 ( ch3_xy_dsp_dout13 )
|
|
,.DATA_IN14 ( ch3_xy_dsp_dout14 )
|
|
,.DATA_IN15 ( ch3_xy_dsp_dout15 )
|
|
|
|
,.A_DEM_MSB_OUT0 ( ch3_xy_A_DEM_MSB_OUT0 )
|
|
,.A_DEM_MSB_OUT1 ( ch3_xy_A_DEM_MSB_OUT1 )
|
|
,.A_DEM_MSB_OUT2 ( ch3_xy_A_DEM_MSB_OUT2 )
|
|
,.A_DEM_MSB_OUT3 ( ch3_xy_A_DEM_MSB_OUT3 )
|
|
,.A_DEM_MSB_OUT4 ( ch3_xy_A_DEM_MSB_OUT4 )
|
|
,.A_DEM_MSB_OUT5 ( ch3_xy_A_DEM_MSB_OUT5 )
|
|
,.A_DEM_MSB_OUT6 ( ch3_xy_A_DEM_MSB_OUT6 )
|
|
,.A_DEM_MSB_OUT7 ( ch3_xy_A_DEM_MSB_OUT7 )
|
|
|
|
,.A_DEM_ISB_OUT0 ( ch3_xy_A_DEM_ISB_OUT0 )
|
|
,.A_DEM_ISB_OUT1 ( ch3_xy_A_DEM_ISB_OUT1 )
|
|
,.A_DEM_ISB_OUT2 ( ch3_xy_A_DEM_ISB_OUT2 )
|
|
,.A_DEM_ISB_OUT3 ( ch3_xy_A_DEM_ISB_OUT3 )
|
|
,.A_DEM_ISB_OUT4 ( ch3_xy_A_DEM_ISB_OUT4 )
|
|
,.A_DEM_ISB_OUT5 ( ch3_xy_A_DEM_ISB_OUT5 )
|
|
,.A_DEM_ISB_OUT6 ( ch3_xy_A_DEM_ISB_OUT6 )
|
|
,.A_DEM_ISB_OUT7 ( ch3_xy_A_DEM_ISB_OUT7 )
|
|
|
|
,.A_DEM_LSB_OUT0 ( ch3_xy_A_DEM_LSB_OUT0 )
|
|
,.A_DEM_LSB_OUT1 ( ch3_xy_A_DEM_LSB_OUT1 )
|
|
,.A_DEM_LSB_OUT2 ( ch3_xy_A_DEM_LSB_OUT2 )
|
|
,.A_DEM_LSB_OUT3 ( ch3_xy_A_DEM_LSB_OUT3 )
|
|
,.A_DEM_LSB_OUT4 ( ch3_xy_A_DEM_LSB_OUT4 )
|
|
,.A_DEM_LSB_OUT5 ( ch3_xy_A_DEM_LSB_OUT5 )
|
|
,.A_DEM_LSB_OUT6 ( ch3_xy_A_DEM_LSB_OUT6 )
|
|
,.A_DEM_LSB_OUT7 ( ch3_xy_A_DEM_LSB_OUT7 )
|
|
|
|
,.B_DEM_MSB_OUT0 ( ch3_xy_B_DEM_MSB_OUT0 )
|
|
,.B_DEM_MSB_OUT1 ( ch3_xy_B_DEM_MSB_OUT1 )
|
|
,.B_DEM_MSB_OUT2 ( ch3_xy_B_DEM_MSB_OUT2 )
|
|
,.B_DEM_MSB_OUT3 ( ch3_xy_B_DEM_MSB_OUT3 )
|
|
,.B_DEM_MSB_OUT4 ( ch3_xy_B_DEM_MSB_OUT4 )
|
|
,.B_DEM_MSB_OUT5 ( ch3_xy_B_DEM_MSB_OUT5 )
|
|
,.B_DEM_MSB_OUT6 ( ch3_xy_B_DEM_MSB_OUT6 )
|
|
,.B_DEM_MSB_OUT7 ( ch3_xy_B_DEM_MSB_OUT7 )
|
|
|
|
,.B_DEM_ISB_OUT0 ( ch3_xy_B_DEM_ISB_OUT0 )
|
|
,.B_DEM_ISB_OUT1 ( ch3_xy_B_DEM_ISB_OUT1 )
|
|
,.B_DEM_ISB_OUT2 ( ch3_xy_B_DEM_ISB_OUT2 )
|
|
,.B_DEM_ISB_OUT3 ( ch3_xy_B_DEM_ISB_OUT3 )
|
|
,.B_DEM_ISB_OUT4 ( ch3_xy_B_DEM_ISB_OUT4 )
|
|
,.B_DEM_ISB_OUT5 ( ch3_xy_B_DEM_ISB_OUT5 )
|
|
,.B_DEM_ISB_OUT6 ( ch3_xy_B_DEM_ISB_OUT6 )
|
|
,.B_DEM_ISB_OUT7 ( ch3_xy_B_DEM_ISB_OUT7 )
|
|
|
|
,.B_DEM_LSB_OUT0 ( ch3_xy_B_DEM_LSB_OUT0 )
|
|
,.B_DEM_LSB_OUT1 ( ch3_xy_B_DEM_LSB_OUT1 )
|
|
,.B_DEM_LSB_OUT2 ( ch3_xy_B_DEM_LSB_OUT2 )
|
|
,.B_DEM_LSB_OUT3 ( ch3_xy_B_DEM_LSB_OUT3 )
|
|
,.B_DEM_LSB_OUT4 ( ch3_xy_B_DEM_LSB_OUT4 )
|
|
,.B_DEM_LSB_OUT5 ( ch3_xy_B_DEM_LSB_OUT5 )
|
|
,.B_DEM_LSB_OUT6 ( ch3_xy_B_DEM_LSB_OUT6 )
|
|
,.B_DEM_LSB_OUT7 ( ch3_xy_B_DEM_LSB_OUT7 )
|
|
);
|
|
`endif
|
|
//------------------------------XY ch3 DAC_DEM_16 instantiation end----------------------------
|
|
// DAC_DEM_16
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
//------------------------------Z ch3 DAC_DEM_16 instantiation start---------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`ifdef CHANNEL_Z_ON
|
|
DAC_DEM_4 U3_DAC_DEM_4 (
|
|
.CLK_IN ( clk )
|
|
,.prbs_en ( ch3_dac_Prbs )
|
|
,.set0 ( ch3_dac_Set0 )
|
|
,.set1 ( ch3_dac_Set1 )
|
|
,.set2 ( ch3_dac_Set2 )
|
|
,.set3 ( ch3_dac_Set3 )
|
|
,.DATA_IN0 ( ch3_z_dsp_dout0 )
|
|
,.DATA_IN1 ( ch3_z_dsp_dout1 )
|
|
,.DATA_IN2 ( ch3_z_dsp_dout2 )
|
|
,.DATA_IN3 ( ch3_z_dsp_dout3 )
|
|
,.DEM_MSB_OUT0 ( ch3_z_DEM_MSB_OUT0 )
|
|
,.DEM_MSB_OUT1 ( ch3_z_DEM_MSB_OUT1 )
|
|
,.DEM_MSB_OUT2 ( ch3_z_DEM_MSB_OUT2 )
|
|
,.DEM_MSB_OUT3 ( ch3_z_DEM_MSB_OUT3 )
|
|
,.DEM_ISB_OUT0 ( ch3_z_DEM_ISB_OUT0 )
|
|
,.DEM_ISB_OUT1 ( ch3_z_DEM_ISB_OUT1 )
|
|
,.DEM_ISB_OUT2 ( ch3_z_DEM_ISB_OUT2 )
|
|
,.DEM_ISB_OUT3 ( ch3_z_DEM_ISB_OUT3 )
|
|
,.DEM_LSB_OUT0 ( ch3_z_DEM_LSB_OUT0 )
|
|
,.DEM_LSB_OUT1 ( ch3_z_DEM_LSB_OUT1 )
|
|
,.DEM_LSB_OUT2 ( ch3_z_DEM_LSB_OUT2 )
|
|
,.DEM_LSB_OUT3 ( ch3_z_DEM_LSB_OUT3 )
|
|
);
|
|
`endif
|
|
//------------------------------Z ch3 DAC_DEM instantiation end-----------------------------
|
|
// DAC_DEM_4
|
|
//---------------------------------------------------------------------------------------------
|
|
|
|
`endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule |