75 lines
2.9 KiB
Verilog
75 lines
2.9 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu_regfile.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY The Regfile module to implement the core's general purpose registers file
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu_regfile(
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input clk
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,input rst_n
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,input [`QBMCU_RFIDX_WIDTH-1:0] read_src1_idx
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,input [`QBMCU_RFIDX_WIDTH-1:0] read_src2_idx
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,output [`QBMCU_XLEN-1 :0] read_src1_dat
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,output [`QBMCU_XLEN-1 :0] read_src2_dat
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,input wbck_dest_wen
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,input [`QBMCU_RFIDX_WIDTH-1:0] wbck_dest_idx
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,input [`QBMCU_XLEN-1 :0] wbck_dest_dat
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);
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wire [`QBMCU_XLEN-1 :0] rf_r [`QBMCU_RFREG_NUM-1:0];
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wire [`QBMCU_RFREG_NUM-1:0] rf_wen;
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genvar i;
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generate //{
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for (i=0; i<`QBMCU_RFREG_NUM; i=i+1) begin:regfile//{
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if(i==0) begin: rf0
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// x0 cannot be wrote since it is constant-zeros
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assign rf_wen[i] = 1'b0;
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assign rf_r[i] = `QBMCU_XLEN'b0;
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end
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else begin: rfno0
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assign rf_wen[i] = wbck_dest_wen & (wbck_dest_idx == i) ;
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sirv_gnrl_dfflr #(`QBMCU_XLEN) rf_dfflr (rf_wen[i], wbck_dest_dat, rf_r[i], clk, rst_n);
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end
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end//}
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endgenerate//}
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assign read_src1_dat = rf_r[read_src1_idx];
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assign read_src2_dat = rf_r[read_src2_idx];
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endmodule
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`include "qbmcu_undefines.v" |