119 lines
4.6 KiB
Verilog
119 lines
4.6 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu_ifu.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY The ifetch module to generate next PC and bus request
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu_ifu(
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input clk // System Clock
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,input rst_n // System reset,active low
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,input ifu_active // IFU module Active from MCU FSM
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,input exu_active // IFU module Active from MCU FSM
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,input [`QBMCU_PC_SIZE-1 :0] pc_rtvec // Initial PC
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,output [`QBMCU_PC_SIZE-1 :0] ifu_req_pc // Fetch PC
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,output ifu_req // Fetch req
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,input [`QBMCU_INSTR_SIZE-1:0] ifu_rsp_instr // Response instruction
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// The IR stage to DEC interface
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,output [`QBMCU_INSTR_SIZE-1:0] ifu_o_ir // The instruction register
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,output [`QBMCU_PC_SIZE-1 :0] ifu_o_pc // The PC register along with
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,input ifupc_rst
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,input update_pc_req
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,input [`QBMCU_PC_SIZE-1 :0] update_pc_value
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);
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wire ifu_req_w;
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wire [`QBMCU_PC_SIZE-1 :0] pc_r;
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//wire pc_ena;
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//wire [`QBMCU_INSTR_SIZE-1 :0] ifu_ir_r;// The instruction register
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//wire [`QBMCU_PC_SIZE-1 :0] ifu_pc_r;// The PC register
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wire [`QBMCU_PC_SIZE-1:0] pc_nxt_pre;
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wire [`QBMCU_PC_SIZE-1:0] pc_nxt;
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//ifu_req
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assign ifu_req_w = ifu_active;
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wire [`QBMCU_PC_SIZE-1:0] pc_add_op1 =
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(rst_n == 1'b0 | ifupc_rst) ? pc_rtvec :
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pc_r;
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wire [`QBMCU_PC_SIZE-1:0] pc_add_op2 =
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(rst_n == 1'b0 | ifupc_rst) ? `QBMCU_PC_SIZE'b0 :
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32'h4 ;
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assign pc_nxt_pre = pc_add_op1 + pc_add_op2;
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//pc_nxt
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assign pc_nxt = update_pc_req ? {update_pc_value[`QBMCU_PC_SIZE-1:1],1'b0} :
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{pc_nxt_pre[`QBMCU_PC_SIZE-1:1] ,1'b0};
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// The PC will need to be updated when MCU's FSM is IFU status
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//sirv_gnrl_dffr #(1) pc_ena_dffr (ifu_active, pc_ena, clk, rst_n);
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//pc_r
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sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) pc_dfflr (exu_active, pc_nxt, pc_r, clk, rst_n & ~ifupc_rst);
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/*
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) begin
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pc_r <= `QBMCU_PC_SIZE'h0;
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end
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else if(ifupc_rst) begin
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pc_r <= `QBMCU_PC_SIZE'h0;
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end
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else if(exu_active) begin
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pc_r <= pc_nxt;
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end
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end
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*/
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// IFU-IR loaded with the returned instruction from the IFetch RSP channel
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wire [`QBMCU_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;
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//ifu_ir_r
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//sirv_gnrl_dfflr #(`QBMCU_INSTR_SIZE) ifu_ir_dfflr (ifu_active, ifu_ir_nxt, ifu_ir_r, clk, rst_n);
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//ifu_pc_r
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//sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) ifu_pc_dfflr (ifu_active, pc_r, ifu_pc_r, clk, rst_n);
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//ifu_req_pc
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assign ifu_req_pc = pc_r;
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assign ifu_req = ifu_req_w;
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//assign ifu_req = pc_ena;
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assign ifu_o_ir = ifu_ir_nxt;
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assign ifu_o_pc = pc_r;
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endmodule
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`include "qbmcu_undefines.v" |