113 lines
4.3 KiB
Verilog
113 lines
4.3 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu_fsm.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY The ifetch module to generate next PC and bus request
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu_fsm (
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input clk
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,input rst_n
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,input start
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,input exit
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,input ext_wait
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,input qbmcu_timer_done
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,input dec_ilegl
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,input agu_addr_unalgn
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,output ifupc_rst
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,output ifu_active
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,output wb_active
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,output dec_active
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,output exu_active
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,output [2:0] qbmcu_fsm_st
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);
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localparam IDLE = 3'b000,
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IFUWB = 3'b001,
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DEC = 3'b010,
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EXU = 3'b011,
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WAIT = 3'b100;
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wire [2:0] state_c;
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wire [2:0] state_n;
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wire ilde2ifuwb;
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wire ifuwb2dec;
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wire dec2exu;
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wire exu2ifuwb;
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wire exu2idle;
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wire exu2wait;
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wire wait2ifuwb;
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//The first section of the state machine
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//state_c
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sirv_gnrl_dffr #(3) state_c_dffr (state_n, state_c, clk, rst_n);
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//////////////////////////////////////////////////////////////
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//fsm
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//////////////////////////////////////////////////////////////
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//state_n
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assign state_n = //(rst_n == 1'b0) ? IDLE :
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((state_c == IDLE ) && ilde2ifuwb) ? IFUWB :
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((state_c == IFUWB) && ifuwb2dec ) ? DEC :
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((state_c == DEC ) && dec2exu ) ? EXU :
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((state_c == EXU ) && exu2idle ) ? IDLE :
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((state_c == EXU ) && exu2ifuwb ) ? IFUWB :
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((state_c == EXU ) && exu2wait ) ? WAIT :
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((state_c == WAIT ) && wait2ifuwb) ? IFUWB :
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state_c ;
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//Generating jump conditions for state machines
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assign ilde2ifuwb = (state_c == IDLE ) && start;
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assign ifuwb2dec = (state_c == IFUWB) ;
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assign dec2exu = (state_c == DEC ) ;
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assign exu2ifuwb = (state_c == EXU ) && !ext_wait && !(exit | dec_ilegl | agu_addr_unalgn);
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assign exu2wait = (state_c == EXU ) && ext_wait && !(exit | dec_ilegl | agu_addr_unalgn);
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assign exu2idle = (state_c == EXU ) && (exit | dec_ilegl | agu_addr_unalgn);
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assign wait2ifuwb = (state_c == WAIT ) && qbmcu_timer_done ;
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//Output signal generation
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//ifupc_rst
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sirv_gnrl_dffr #(1) ifupc_rst_dffr (exu2idle, ifupc_rst, clk, rst_n);
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//ifu_active
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sirv_gnrl_dffr #(1) ifu_active_dffr (ilde2ifuwb | exu2ifuwb | wait2ifuwb, ifu_active, clk, rst_n);
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//wb_active
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sirv_gnrl_dffr #(1) wb_active_dffr (exu2ifuwb | wait2ifuwb, wb_active, clk, rst_n);
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//dec_active
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sirv_gnrl_dffr #(1) dec_active_dffr (ifuwb2dec, dec_active, clk, rst_n);
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//exu_active
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sirv_gnrl_dffr #(1) exu_active_dffr (dec2exu, exu_active, clk, rst_n);
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//qbmcu_fsm_st
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sirv_gnrl_dffr #(3) qbmcu_fsm_st_dffr (state_c, qbmcu_fsm_st, clk, rst_n);
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endmodule
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`include "qbmcu_undefines.v" |