122 lines
5.6 KiB
Verilog
122 lines
5.6 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu_exu_ext.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY This module to implement the regular EXT instructions
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu_exu_ext(
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//system port
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input clk
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,input rst_n
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//////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////
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,input [`QBMCU_XLEN-1 :0] ext_i_rs1
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,input [`QBMCU_XLEN-1 :0] ext_i_imm
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,input [`QBMCU_DECINFO_EXT_WIDTH-1:0] ext_i_info
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,input ext_i_op
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//The enable signal from the master control state machine
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,input ext_i_active
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//////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////
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//
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// The operands and info to peripheral
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,output ext_o_wait_valid
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,output ext_o_wait
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,output [`QBMCU_XLEN-1 :0] ext_o_wait_cnt
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,output ext_o_send
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,output ext_o_sendc
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,output [`QBMCU_XLEN-1 :0] ext_o_codeword
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,output ext_o_exit
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,output ext_o_intr
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,output [`QBMCU_XLEN-1 :0] ext_o_wbck_wdat
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,output ext_o_wbck_valid
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);
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wire [`QBMCU_XLEN-1:0] ext_req_alu_op1 = ext_i_rs1;
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wire [`QBMCU_XLEN-1:0] ext_req_alu_op2 = ext_i_imm;
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wire [`QBMCU_XLEN-1:0] ext_req_alu_res = ext_req_alu_op1 + ext_req_alu_op2;
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wire alu_req_alu_wait = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_WAIT ];
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wire alu_req_alu_send = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SEND ];
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wire alu_req_alu_sendc = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_SENDC ];
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wire alu_req_alu_exit = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXIT ];
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wire alu_req_alu_exiti = ext_i_op & ext_i_info [`QBMCU_DECINFO_EXT_EXITI ];
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//ext_o_codeword
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sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_codeword_dfflr (ext_i_active, ext_req_alu_res, ext_o_codeword, clk, rst_n);
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//ext_o_wait_cnt
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//sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wait_cnt_dfflr (ext_i_active, ext_req_alu_res, ext_o_wait_cnt, clk, rst_n);
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assign ext_o_wait_cnt = ext_req_alu_res;
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//ext_o_wait
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wire ext_wait = ext_i_active & alu_req_alu_wait;
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//sirv_gnrl_dffr #(1) ext_o_wait_dffr (ext_wait, ext_o_wait, clk, rst_n);
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assign ext_o_wait = ext_wait;
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wire ext_o_wait_valid_en = ext_wait | ext_i_active;
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wire ext_o_wait_valid_v = ext_wait ? 1'b1 :
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ext_i_active ? 1'b0 :
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1'b0 ;
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sirv_gnrl_dfflr #(1) ext_o_wait_valid_dfflr (ext_o_wait_valid_en, ext_o_wait_valid_v, ext_o_wait_valid, clk, rst_n);
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//ext_o_send
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wire ext_send = ext_i_active & alu_req_alu_send;
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sirv_gnrl_dffr #(1) ext_o_send_dffr (ext_send, ext_o_send, clk, rst_n);
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//ext_o_sendc
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wire ext_sendc = ext_i_active & alu_req_alu_sendc;
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sirv_gnrl_dffr #(1) ext_o_sendc_dffr (ext_sendc, ext_o_sendc, clk, rst_n);
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//ext_o_exit
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assign ext_o_exit = alu_req_alu_exit | alu_req_alu_exiti;
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//sirv_gnrl_dfflr #(1) ext_o_exit_dfflr (ext_i_active, ext_exit, ext_o_exit, clk, rst_n);
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//ext_o_intr
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wire ext_intr = ext_i_active & alu_req_alu_exiti;
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sirv_gnrl_dffr #(1) ext_o_intr_dffr (ext_intr, ext_o_intr, clk, rst_n);
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/////////////////////////////////////////////////////////////////////////////////////////////
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//
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/////////////////////////////////////////////////////////////////////////////////////////////
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//ext_i_active_r
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wire ext_i_active_r;
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sirv_gnrl_dffr #(1) ext_i_active_r_dffr (ext_i_active, ext_i_active_r, clk, rst_n);
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//ext_o_wbck_wdat
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sirv_gnrl_dfflr #(`QBMCU_XLEN) ext_o_wbck_wdat_dfflr (ext_i_active_r, ext_req_alu_res, ext_o_wbck_wdat, clk, rst_n);
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//ext_o_wbck_valid
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sirv_gnrl_dfflr #(1) ext_o_wbck_valid_dfflr (ext_i_active_r, ext_i_op, ext_o_wbck_valid, clk, rst_n);
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endmodule
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`include "qbmcu_undefines.v" |