134 lines
6.0 KiB
Verilog
134 lines
6.0 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
|
|
// Company:
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// File Name : qbmcu_exu_bjp.v
|
|
// Department :
|
|
// Author : PWY
|
|
// Author's Tel :
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Relese History
|
|
// Version Date Author Description
|
|
// 0.1 2024-03-13 PWY This module to implement the Conditional Branch Instructions,
|
|
// which is mostly share the datapath with ALU adder to resolve the comparasion
|
|
// result to save gatecount to mininum
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Keywords :
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Parameter
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Purpose :
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Target Device:
|
|
// Tool versions:
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Reuse Issues
|
|
// Reset Strategy:
|
|
// Clock Domains:
|
|
// Critical Timing:
|
|
// Asynchronous I/F:
|
|
// Synthesizable (y/n):
|
|
// Other:
|
|
//-FHDR--------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
`include "qbmcu_defines.v"
|
|
|
|
|
|
module qbmcu_exu_bjp(
|
|
//system port
|
|
input clk
|
|
,input rst_n
|
|
//////////////////////////////////////////////////////////////
|
|
//////////////////////////////////////////////////////////////
|
|
// The Handshake Interface
|
|
//
|
|
,input [`QBMCU_XLEN-1 :0] bjp_i_rs1
|
|
,input [`QBMCU_XLEN-1 :0] bjp_i_rs2
|
|
,input [`QBMCU_XLEN-1 :0] bjp_i_imm
|
|
,input [`QBMCU_PC_SIZE-1 :0] bjp_i_pc
|
|
,input [`QBMCU_DECINFO_BJP_WIDTH-1:0] bjp_i_info
|
|
,input bjp_i_op
|
|
//The enable signal from the master control state machine
|
|
,input bjp_i_active
|
|
|
|
//////////////////////////////////////////////////////////////
|
|
//Data sent to the write-back module
|
|
//write back interface
|
|
,output [`QBMCU_XLEN-1 :0] bjp_o_wbck_wdat
|
|
,output bjp_o_wbck_valid
|
|
//////////////////////////////////////////////////////////////
|
|
//update the value of the program counter (PC)
|
|
,output update_pc_req
|
|
,output [`QBMCU_PC_SIZE-1 :0] update_pc_value
|
|
//////////////////////////////////////////////////////////////
|
|
// To share the ALU datapath
|
|
// The operands and info to ALU
|
|
,output [`QBMCU_XLEN-1 :0] bjp_req_alu_op1
|
|
,output [`QBMCU_XLEN-1 :0] bjp_req_alu_op2
|
|
,output bjp_req_alu_cmp_eq
|
|
,output bjp_req_alu_cmp_ne
|
|
,output bjp_req_alu_cmp_lt
|
|
,output bjp_req_alu_cmp_gt
|
|
,output bjp_req_alu_cmp_ltu
|
|
,output bjp_req_alu_cmp_gtu
|
|
,output bjp_req_alu_add
|
|
|
|
,input bjp_req_alu_cmp_res
|
|
,input [`QBMCU_XLEN-1 :0] bjp_req_alu_add_res
|
|
);
|
|
|
|
|
|
wire bxx = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BXX ];
|
|
wire jump = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_JUMP ];
|
|
wire jalr = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_JALR ];
|
|
|
|
wire wbck_link = jump;
|
|
|
|
assign bjp_req_alu_op1 = wbck_link ?
|
|
bjp_i_pc
|
|
: bjp_i_rs1;
|
|
assign bjp_req_alu_op2 = wbck_link ?
|
|
`QBMCU_XLEN'd4
|
|
: bjp_i_rs2;
|
|
|
|
wire cmt_bjp = bxx | jump;
|
|
|
|
|
|
assign bjp_req_alu_cmp_eq = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BEQ ];
|
|
assign bjp_req_alu_cmp_ne = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BNE ];
|
|
assign bjp_req_alu_cmp_lt = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BLT ];
|
|
assign bjp_req_alu_cmp_gt = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BGT ];
|
|
assign bjp_req_alu_cmp_ltu = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BLTU ];
|
|
assign bjp_req_alu_cmp_gtu = bjp_i_op & bjp_i_info [`QBMCU_DECINFO_BJP_BGTU ];
|
|
|
|
assign bjp_req_alu_add = wbck_link;
|
|
|
|
wire cmt_rslv = jump ? 1'b1 : bjp_req_alu_cmp_res;
|
|
|
|
|
|
//bjp_o_wbck_wdat
|
|
sirv_gnrl_dfflr #(`QBMCU_XLEN) bjp_o_wbck_wdat_dfflr (bjp_i_active, bjp_req_alu_add_res, bjp_o_wbck_wdat, clk, rst_n);
|
|
//bjp_o_wbck_valid
|
|
sirv_gnrl_dfflr #(1) bjp_o_wbck_valid_dfflr (bjp_i_active, bjp_i_op, bjp_o_wbck_valid, clk, rst_n);
|
|
|
|
wire [`QBMCU_PC_SIZE-1:0] pc_temp = jalr ? bjp_i_rs1 : bjp_i_pc;
|
|
|
|
wire [`QBMCU_PC_SIZE-1:0] update_pc_value_w = (pc_temp + bjp_i_imm[`QBMCU_PC_SIZE-1:0]);
|
|
wire update_pc_req_w = cmt_bjp & cmt_rslv;
|
|
|
|
//wire bjp_i_active_r;
|
|
//sirv_gnrl_dffr #(1)bjp_i_active_r_dffr (bjp_i_active, bjp_i_active_r, clk, rst_n);
|
|
|
|
//update_pc_vaule
|
|
//sirv_gnrl_dfflr #(`QBMCU_PC_SIZE) update_pc_vaule_dfflr (bjp_i_active_r, update_pc_value_w, update_pc_value, clk, rst_n);
|
|
//update_pc_req
|
|
//sirv_gnrl_dfflr #(1) update_pc_req_dfflr (bjp_i_active_r, update_pc_req_w, update_pc_req, clk, rst_n);
|
|
|
|
assign update_pc_value = update_pc_value_w;
|
|
assign update_pc_req = update_pc_req_w;
|
|
endmodule
|
|
|
|
`include "qbmcu_undefines.v" |