386 lines
24 KiB
Verilog
386 lines
24 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu_exu.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY The EXU module to implement entire Execution Stage
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu_exu(
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//system port
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input clk
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,input rst_n
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//////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////
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// The Handshake Interface
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//
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,input [`QBMCU_XLEN-1 :0] exu_i_rs1
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,input [`QBMCU_XLEN-1 :0] exu_i_rs2
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,input [`QBMCU_XLEN-1 :0] exu_i_imm
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,input [`QBMCU_PC_SIZE-1 :0] exu_i_pc
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,input [`QBMCU_DECINFO_WIDTH-1 :0] exu_i_info
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,input exu_i_ilegl
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//The enable signal from the master control state machine
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,input exu_i_active
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//////////////////////////////////////////////////////////////
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//Data sent to the write-back module
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//write back interface
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,output [`QBMCU_XLEN-1 :0] bjp_o_wbck_wdat
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,output bjp_o_wbck_valid
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//////////////////////////////////////////////////////////////
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//update the value of the program counter (PC)
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,output bjp_update_pc_req
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,output [`QBMCU_PC_SIZE-1 :0] bjp_update_pc_value
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// The operands and info to peripheral
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,output ext_o_wait_valid
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,output ext_o_wait
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,output [`QBMCU_XLEN-1 :0] ext_o_wait_cnt
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,output ext_o_send
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,output ext_o_sendc
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,output [`QBMCU_XLEN-1 :0] ext_o_codeword
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,output ext_o_exit
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,output ext_o_intr
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,output [`QBMCU_XLEN-1 :0] ext_o_wbck_wdat
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,output ext_o_wbck_valid
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//////////////////////////////////////////////////////////////
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//Address, data, and enable signals connected to the memory space
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,output [`QBMCU_ADDR_SIZE-1 :0] agu_o_addr
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,output [`QBMCU_XLEN-1 :0] agu_o_wdata
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,output agu_o_wren // Write enable
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,output agu_o_rden // Read enable
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,output [`QBMCU_XLEN/8-1 :0] agu_o_wmask
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,input [`QBMCU_XLEN-1 :0] agu_i_rdata
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//Data sent to the write-back module
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//write back interface
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,output [`QBMCU_XLEN-1 :0] agu_o_wbck_wdat
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,output agu_o_wbck_valid
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//Misaligned memory address
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,output agu_o_addr_unalgn
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// The Write-Back Interface for Special (unaligned ldst instructions)
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,output [`QBMCU_XLEN-1 :0] alu_o_wbck_wdat
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,output alu_o_wbck_valid
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//AGU
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire [`QBMCU_XLEN-1 :0] agu_i_rs1 ;
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wire [`QBMCU_XLEN-1 :0] agu_i_rs2 ;
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wire [`QBMCU_XLEN-1 :0] agu_i_imm ;
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wire [`QBMCU_DECINFO_WIDTH-1 :0] agu_i_info ;
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wire agu_i_op ;
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//qbmcu_datalatch_agu
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qbmcu_datalatch #(
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.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_AGU )
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) U_qubitmcu_datalatch_agu
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(
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.i_rs1 ( exu_i_rs1 )
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,.i_rs2 ( exu_i_rs2 )
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,.i_imm ( exu_i_imm )
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,.i_info ( exu_i_info )
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,.i_pc ( exu_i_pc )
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,.i_ilegl ( exu_i_ilegl )
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,.o_rs1 ( agu_i_rs1 )
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,.o_rs2 ( agu_i_rs2 )
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,.o_imm ( agu_i_imm )
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,.o_info ( agu_i_info )
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,.o_pc ( )
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,.o_op ( agu_i_op )
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);
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//qbmcu_exu_lsuagu
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qbmcu_exu_lsuagu U_qbmcu_exu_lsuagu (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.agu_i_rs1 ( agu_i_rs1 )
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,.agu_i_rs2 ( agu_i_rs2 )
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,.agu_i_imm ( agu_i_imm )
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,.agu_i_info ( agu_i_info[`QBMCU_DECINFO_AGU_WIDTH-1:0])
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,.agu_i_op ( agu_i_op )
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,.agu_i_active ( exu_i_active )
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,.agu_o_addr ( agu_o_addr )
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,.agu_o_wdata ( agu_o_wdata )
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,.agu_o_wren ( agu_o_wren )
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,.agu_o_rden ( agu_o_rden )
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,.agu_o_wmask ( agu_o_wmask )
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,.agu_i_rdata ( agu_i_rdata )
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,.agu_o_wbck_wdat ( agu_o_wbck_wdat )
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,.agu_o_wbck_valid ( agu_o_wbck_valid )
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,.agu_o_addr_unalgn ( agu_o_addr_unalgn )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//EXT
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire [`QBMCU_XLEN-1 :0] ext_i_rs1 ;
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wire [`QBMCU_XLEN-1 :0] ext_i_imm ;
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wire [`QBMCU_DECINFO_WIDTH-1 :0] ext_i_info ;
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wire ext_i_op ;
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//qbmcu_datalatch_ext
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qbmcu_datalatch #(
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.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_EXT )
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) U_qubitmcu_datalatch_ext
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(
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.i_rs1 ( exu_i_rs1 )
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,.i_rs2 ( exu_i_rs2 )
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,.i_imm ( exu_i_imm )
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,.i_info ( exu_i_info )
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,.i_pc ( exu_i_pc )
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,.i_ilegl ( exu_i_ilegl )
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,.o_rs1 ( ext_i_rs1 )
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,.o_rs2 ( )
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,.o_imm ( ext_i_imm )
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,.o_info ( ext_i_info )
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,.o_pc ( )
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,.o_op ( ext_i_op )
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);
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//qbmcu_exu_ext
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qbmcu_exu_ext U_qbmcu_exu_ext (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.ext_i_rs1 ( ext_i_rs1 )
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,.ext_i_imm ( ext_i_imm )
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,.ext_i_info ( ext_i_info[`QBMCU_DECINFO_EXT_WIDTH-1:0])
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,.ext_i_op ( ext_i_op )
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,.ext_o_wait_valid ( ext_o_wait_valid )
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,.ext_i_active ( exu_i_active )
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,.ext_o_wait ( ext_o_wait )
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,.ext_o_wait_cnt ( ext_o_wait_cnt )
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,.ext_o_send ( ext_o_send )
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,.ext_o_sendc ( ext_o_sendc )
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,.ext_o_codeword ( ext_o_codeword )
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,.ext_o_exit ( ext_o_exit )
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,.ext_o_intr ( ext_o_intr )
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,.ext_o_wbck_wdat ( ext_o_wbck_wdat )
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,.ext_o_wbck_valid ( ext_o_wbck_valid )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//BJP
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire [`QBMCU_XLEN-1 :0] bjp_i_rs1 ;
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wire [`QBMCU_XLEN-1 :0] bjp_i_rs2 ;
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wire [`QBMCU_XLEN-1 :0] bjp_i_imm ;
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wire [`QBMCU_DECINFO_WIDTH-1 :0] bjp_i_info ;
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wire [`QBMCU_PC_SIZE-1 :0] bjp_i_pc ;
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wire bjp_i_op ;
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//////////////////////////////////////////////////////////////
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// To share the ALU datapath
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// The operands and info to ALU
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wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op1 ;
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wire [`QBMCU_XLEN-1 :0] bjp_req_alu_op2 ;
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wire bjp_req_alu_cmp_eq ;
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wire bjp_req_alu_cmp_ne ;
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wire bjp_req_alu_cmp_lt ;
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wire bjp_req_alu_cmp_gt ;
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wire bjp_req_alu_cmp_ltu ;
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wire bjp_req_alu_cmp_gtu ;
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wire bjp_req_alu_add ;
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wire bjp_req_alu_cmp_res ;
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wire [`QBMCU_XLEN-1 :0] bjp_req_alu_add_res ;
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//qbmcu_datalatch_bjp
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qbmcu_datalatch #(
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.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_BJP )
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) U_qubitmcu_datalatch_bjp
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(
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.i_rs1 ( exu_i_rs1 )
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,.i_rs2 ( exu_i_rs2 )
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,.i_imm ( exu_i_imm )
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,.i_info ( exu_i_info )
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,.i_pc ( exu_i_pc )
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,.i_ilegl ( exu_i_ilegl )
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,.o_rs1 ( bjp_i_rs1 )
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,.o_rs2 ( bjp_i_rs2 )
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,.o_imm ( bjp_i_imm )
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,.o_info ( bjp_i_info )
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,.o_pc ( bjp_i_pc )
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,.o_op ( bjp_i_op )
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);
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//qbmcu_exu_bjp
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qbmcu_exu_bjp U_qbmcu_exu_bjp (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.bjp_i_rs1 ( bjp_i_rs1 )
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,.bjp_i_rs2 ( bjp_i_rs2 )
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,.bjp_i_imm ( bjp_i_imm )
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,.bjp_i_pc ( bjp_i_pc )
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,.bjp_i_info ( bjp_i_info[`QBMCU_DECINFO_BJP_WIDTH-1:0])
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,.bjp_i_op ( bjp_i_op )
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,.bjp_i_active ( exu_i_active )
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,.bjp_o_wbck_valid ( bjp_o_wbck_valid )
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,.bjp_o_wbck_wdat ( bjp_o_wbck_wdat )
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,.update_pc_req ( bjp_update_pc_req )
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,.update_pc_value ( bjp_update_pc_value )
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,.bjp_req_alu_op1 ( bjp_req_alu_op1 )
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,.bjp_req_alu_op2 ( bjp_req_alu_op2 )
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,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq )
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,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne )
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,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt )
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,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt )
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,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu )
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,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu )
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,.bjp_req_alu_add ( bjp_req_alu_add )
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,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res )
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,.bjp_req_alu_add_res ( bjp_req_alu_add_res )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//ALU
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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wire [`QBMCU_XLEN-1 :0] alu_i_rs1 ;
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wire [`QBMCU_XLEN-1 :0] alu_i_rs2 ;
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wire [`QBMCU_XLEN-1 :0] alu_i_imm ;
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wire [`QBMCU_DECINFO_WIDTH-1 :0] alu_i_info ;
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wire [`QBMCU_PC_SIZE-1 :0] alu_i_pc ;
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wire alu_i_op ;
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//////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////
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// To share the ALU datapath
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//
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// The operands and info to ALU
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wire alu_req_alu_add ;
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wire alu_req_alu_sub ;
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wire alu_req_alu_xor ;
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wire alu_req_alu_sll ;
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wire alu_req_alu_srl ;
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wire alu_req_alu_sra ;
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wire alu_req_alu_or ;
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wire alu_req_alu_and ;
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wire alu_req_alu_slt ;
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wire alu_req_alu_sltu ;
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wire alu_req_alu_lui ;
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wire [`QBMCU_XLEN-1 :0] alu_req_alu_op1 ;
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wire [`QBMCU_XLEN-1 :0] alu_req_alu_op2 ;
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wire [`QBMCU_XLEN-1 :0] alu_req_alu_res ;
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//qbmcu_datalatch_alu
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qbmcu_datalatch #(
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.DECINFO_GRP_OP ( `QBMCU_DECINFO_GRP_ALU )
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) U_qbmcu_datalatch_alu
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(
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.i_rs1 ( exu_i_rs1 )
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,.i_rs2 ( exu_i_rs2 )
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,.i_imm ( exu_i_imm )
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,.i_info ( exu_i_info )
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,.i_pc ( exu_i_pc )
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,.i_ilegl ( exu_i_ilegl )
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,.o_rs1 ( alu_i_rs1 )
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,.o_rs2 ( alu_i_rs2 )
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,.o_imm ( alu_i_imm )
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,.o_info ( alu_i_info )
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,.o_pc ( alu_i_pc )
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,.o_op ( alu_i_op )
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);
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//qbmcu_exu_alu_rglr
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qbmcu_exu_alu U_qbmcu_exu_alu (
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.clk ( clk )
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,.rst_n ( rst_n )
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,.alu_i_rs1 ( alu_i_rs1 )
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,.alu_i_rs2 ( alu_i_rs2 )
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,.alu_i_imm ( alu_i_imm )
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,.alu_i_pc ( alu_i_pc )
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,.alu_i_info ( alu_i_info[`QBMCU_DECINFO_ALU_WIDTH-1:0])
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,.alu_i_op ( alu_i_op )
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,.alu_i_active ( exu_i_active )
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,.alu_o_wbck_wdat ( alu_o_wbck_wdat )
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,.alu_o_wbck_valid ( alu_o_wbck_valid )
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,.alu_req_alu_add ( alu_req_alu_add )
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,.alu_req_alu_sub ( alu_req_alu_sub )
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,.alu_req_alu_xor ( alu_req_alu_xor )
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,.alu_req_alu_sll ( alu_req_alu_sll )
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,.alu_req_alu_srl ( alu_req_alu_srl )
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,.alu_req_alu_sra ( alu_req_alu_sra )
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,.alu_req_alu_or ( alu_req_alu_or )
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,.alu_req_alu_and ( alu_req_alu_and )
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,.alu_req_alu_slt ( alu_req_alu_slt )
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,.alu_req_alu_sltu ( alu_req_alu_sltu )
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,.alu_req_alu_lui ( alu_req_alu_lui )
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,.alu_req_alu_op1 ( alu_req_alu_op1 )
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,.alu_req_alu_op2 ( alu_req_alu_op2 )
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,.alu_req_alu_res ( alu_req_alu_res )
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//DPATH
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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qbmcu_exu_dpath U_qbmcu_exu_dpath (
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.alu_req_alu ( alu_i_op )
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,.alu_req_alu_add ( alu_req_alu_add )
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,.alu_req_alu_sub ( alu_req_alu_sub )
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,.alu_req_alu_xor ( alu_req_alu_xor )
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,.alu_req_alu_sll ( alu_req_alu_sll )
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,.alu_req_alu_srl ( alu_req_alu_srl )
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,.alu_req_alu_sra ( alu_req_alu_sra )
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,.alu_req_alu_or ( alu_req_alu_or )
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,.alu_req_alu_and ( alu_req_alu_and )
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,.alu_req_alu_slt ( alu_req_alu_slt )
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,.alu_req_alu_sltu ( alu_req_alu_sltu )
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,.alu_req_alu_lui ( alu_req_alu_lui )
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,.alu_req_alu_op1 ( alu_req_alu_op1 )
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,.alu_req_alu_op2 ( alu_req_alu_op2 )
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,.alu_req_alu_res ( alu_req_alu_res )
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,.bjp_req_alu ( bjp_i_op )
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,.bjp_req_alu_op1 ( bjp_req_alu_op1 )
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,.bjp_req_alu_op2 ( bjp_req_alu_op2 )
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,.bjp_req_alu_cmp_eq ( bjp_req_alu_cmp_eq )
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,.bjp_req_alu_cmp_ne ( bjp_req_alu_cmp_ne )
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,.bjp_req_alu_cmp_lt ( bjp_req_alu_cmp_lt )
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,.bjp_req_alu_cmp_gt ( bjp_req_alu_cmp_gt )
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,.bjp_req_alu_cmp_ltu ( bjp_req_alu_cmp_ltu )
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,.bjp_req_alu_cmp_gtu ( bjp_req_alu_cmp_gtu )
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,.bjp_req_alu_add ( bjp_req_alu_add )
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,.bjp_req_alu_cmp_res ( bjp_req_alu_cmp_res )
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,.bjp_req_alu_add_res ( bjp_req_alu_add_res )
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);
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endmodule
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`include "qbmcu_undefines.v"
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