69 lines
2.9 KiB
Verilog
69 lines
2.9 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : qbmcu_datalatch.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY The operation of latch and hold, eliminating invalid toggling to
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// reduce dynamic power consumption.
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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`include "qbmcu_defines.v"
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module qbmcu_datalatch #(
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parameter DECINFO_GRP_OP = `QBMCU_DECINFO_GRP_AGU )
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(
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input [`QBMCU_XLEN-1 :0] i_rs1
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,input [`QBMCU_XLEN-1 :0] i_rs2
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,input [`QBMCU_XLEN-1 :0] i_imm
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,input [`QBMCU_DECINFO_WIDTH-1 :0] i_info
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,input [`QBMCU_PC_SIZE-1 :0] i_pc
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,input i_ilegl
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,output [`QBMCU_XLEN-1 :0] o_rs1
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,output [`QBMCU_XLEN-1 :0] o_rs2
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,output [`QBMCU_XLEN-1 :0] o_imm
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,output [`QBMCU_DECINFO_WIDTH-1 :0] o_info
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,output [`QBMCU_PC_SIZE-1 :0] o_pc
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,output o_op
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);
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wire op = (~i_ilegl) & (i_info[`QBMCU_DECINFO_GRP] == DECINFO_GRP_OP);
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assign o_rs1 = {`QBMCU_XLEN {op}} & i_rs1 ;
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assign o_rs2 = {`QBMCU_XLEN {op}} & i_rs2 ;
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assign o_imm = {`QBMCU_XLEN {op}} & i_imm ;
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assign o_info = {`QBMCU_DECINFO_WIDTH{op}} & i_info ;
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assign o_pc = {`QBMCU_PC_SIZE {op}} & i_pc ;
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assign o_op = op;
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endmodule
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`include "qbmcu_undefines.v" |