127 lines
3.4 KiB
Verilog
127 lines
3.4 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1994 - 2015 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: Anatoly Sokhatsky July 10, 1994
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//
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// VERSION: Simulation Architecture
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//
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// DesignWare_version: 0781642f
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// DesignWare_release: K-2015.06-DWBB_201506.0
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Up/Down Counter
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// parameterizable wordlength (width > 0)
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// clk - positive edge-triggering clock
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// reset - asynchronous reset (active low)
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// data - data load input
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// cen - counter enable
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// count - counter state
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//
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// MODIFIED : GN Feb. 16th, 1996
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// changed dw03 to DW03
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// remove $generic
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// defined paramter = 8
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//
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// RJK June 19, 1997
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// Corrected faulty tercnt detection mechanism
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//
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// Rong Sep. 1999
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// Add x-handling
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//
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// RJK May 17, 2000
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// Updated to latest coding style to avoid blocking vs.
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// nonblocking assignment problems (STAR 103980)
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//-------------------------------------------------------------------------------
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module DW03_updn_ctr (
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// input ports
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data, // data used for load operation
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up_dn, // up/down control input (0=down, 1-up)
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load, // load operation control input (active low)
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cen, // count enable control input (active high enable)
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clk, // clock input
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reset, // asynchronous reset input (active low)
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// output ports
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count, // count value output
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tercnt // terminal count output flag (active high)
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);
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parameter width = 8;
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// port list declaration in order
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input [width-1 : 0] data;
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input up_dn, load, cen, clk, reset;
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output [width-1 : 0] count;
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output tercnt;
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// synopsys translate_off
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reg [width-1 : 0] cur_state;
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wire [width-1 : 0] next_state;
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assign count = cur_state;
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always @ (posedge clk or negedge reset) begin : P_clk_registers
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if (reset === 1'b0)
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cur_state <= {width{1'b0}};
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else begin
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if (reset === 1'b1)
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cur_state <= next_state;
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else
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cur_state <= {width{reset ^ reset}};
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end
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end // P_clk_registers
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assign next_state = (load == 1'b0)? data | {width{1'b0}} :
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( (cen == 1'b0)? cur_state :
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( (up_dn == 1'b0)? cur_state + {width{1'b1}} :
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cur_state - {width{1'b1}} ) );
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assign tercnt = (up_dn == 1'b0)? ( (cur_state == {width{1'b0}})? 1'b1 : 1'b0 ) :
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( (cur_state == {width{1'b1}})? 1'b1 : 1'b0 );
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initial begin : parameter_check
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if ( width < 1 ) begin
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter width (lower bound: 1 )",
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width );
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$finish;
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end
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end // parameter_check
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always @ (clk) begin : P_monitor_clk
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if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
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$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
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$time, clk );
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end // P_monitor_clk
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// synopsys translate_on
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endmodule // DW03_updn_ctr
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