241 lines
7.0 KiB
Verilog
241 lines
7.0 KiB
Verilog
module NCO(
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clk,
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rstn,
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phase_manual_clr,
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phase_auto_clr,
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fcw,
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pha,
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cos_0,
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cos_1,
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cos_2,
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cos_3,
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cos_4,
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cos_5,
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cos_6,
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cos_7,
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cos_8,
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cos_9,
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cos_10,
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cos_11,
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cos_12,
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cos_13,
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cos_14,
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cos_15,
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sin_0,
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sin_1,
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sin_2,
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sin_3,
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sin_4,
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sin_5,
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sin_6,
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sin_7,
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sin_8,
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sin_9,
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sin_10,
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sin_11,
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sin_12,
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sin_13,
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sin_14,
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sin_15
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);
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input clk;
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input rstn;
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input phase_manual_clr;
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input phase_auto_clr;
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input [47:0] fcw;
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input [15:0] pha;
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output [15:0] cos_0;
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output [15:0] cos_1;
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output [15:0] cos_2;
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output [15:0] cos_3;
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output [15:0] cos_4;
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output [15:0] cos_5;
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output [15:0] cos_6;
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output [15:0] cos_7;
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output [15:0] cos_8;
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output [15:0] cos_9;
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output [15:0] cos_10;
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output [15:0] cos_11;
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output [15:0] cos_12;
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output [15:0] cos_13;
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output [15:0] cos_14;
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output [15:0] cos_15;
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output [15:0] sin_0;
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output [15:0] sin_1;
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output [15:0] sin_2;
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output [15:0] sin_3;
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output [15:0] sin_4;
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output [15:0] sin_5;
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output [15:0] sin_6;
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output [15:0] sin_7;
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output [15:0] sin_8;
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output [15:0] sin_9;
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output [15:0] sin_10;
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output [15:0] sin_11;
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output [15:0] sin_12;
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output [15:0] sin_13;
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output [15:0] sin_14;
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output [15:0] sin_15;
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reg [47:0] fcw1_r1;
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reg [47:0] fcw2_r1;
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reg [47:0] fcw3_r1;
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reg [47:0] fcw4_r1;
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reg [47:0] fcw5_r1;
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reg [47:0] fcw6_r1;
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reg [47:0] fcw7_r1;
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reg [47:0] fcw8_r1;
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reg [47:0] fcw9_r1;
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reg [47:0] fcw10_r1;
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reg [47:0] fcw11_r1;
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reg [47:0] fcw12_r1;
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reg [47:0] fcw13_r1;
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reg [47:0] fcw14_r1;
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reg [47:0] fcw15_r1;
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reg [47:0] fcw16_r1;
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wire [47:0] fcw2_w;
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wire [47:0] fcw4_w;
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wire [47:0] fcw8_w;
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wire [47:0] fcw16_w;
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reg [15:0] pha_r;
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assign fcw2_w=fcw<<3'd1;
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assign fcw4_w=fcw<<3'd2;
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assign fcw8_w=fcw<<3'd3;
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assign fcw16_w=fcw<<3'd4;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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fcw1_r1 <=48'd0;
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fcw2_r1 <=48'd0;
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fcw3_r1 <=48'd0;
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fcw4_r1 <=48'd0;
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fcw5_r1 <=48'd0;
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fcw6_r1 <=48'd0;
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fcw7_r1 <=48'd0;
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fcw8_r1 <=48'd0;
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fcw9_r1 <=48'd0;
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fcw10_r1 <=48'd0;
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fcw11_r1 <=48'd0;
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fcw12_r1 <=48'd0;
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fcw13_r1 <=48'd0;
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fcw14_r1 <=48'd0;
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fcw15_r1 <=48'd0;
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fcw16_r1 <=48'd0;
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end
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else
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begin
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fcw1_r1 <=fcw;
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fcw2_r1 <=fcw2_w;
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fcw3_r1 <=fcw2_w+fcw;
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fcw4_r1 <=fcw4_w;
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fcw5_r1 <=fcw4_w+fcw;
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fcw6_r1 <=fcw4_w+fcw2_w;
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fcw7_r1 <=fcw8_w-fcw;
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fcw8_r1 <=fcw8_w;
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fcw9_r1 <=fcw8_w+fcw;
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fcw10_r1 <=fcw8_w+fcw2_w;
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fcw11_r1 <=fcw8_w+fcw2_w+fcw;
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fcw12_r1 <=fcw8_w+fcw4_w;
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fcw13_r1 <=fcw8_w+fcw4_w+fcw;
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fcw14_r1 <=fcw16_w-fcw2_w;
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fcw15_r1 <=fcw16_w-fcw;
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fcw16_r1 <=fcw16_w;
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end
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always @(posedge clk or negedge rstn) begin
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if(!rstn) begin
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pha_r <= 16'd0;
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end
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else begin
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pha_r <= pha;
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end
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end
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wire clr_acc;
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wire clr_fix;
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assign clr_acc = phase_auto_clr | phase_manual_clr;
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assign clr_fix = phase_manual_clr;
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wire [15:0] s1_i_o;
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wire [15:0] s2_i_o;
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wire [15:0] s3_i_o;
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P_NCO inst_p_nco(
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.clk (clk ),
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.rstn (rstn ),
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.clr (clr_fix ),
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.clr_acc (clr_acc ),
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.pha (pha_r ),
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.s1 (s1_i_o ),
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.s2 (s2_i_o ),
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.s3 (s3_i_o ),
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.s1_o (s1_i_o ),
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.s2_o (s2_i_o ),
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.s3_o (s3_i_o ),
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.fcw1 (fcw1_r1 ),
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.fcw2 (fcw2_r1 ),
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.fcw3 (fcw3_r1 ),
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.fcw4 (fcw4_r1 ),
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.fcw5 (fcw5_r1 ),
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.fcw6 (fcw6_r1 ),
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.fcw7 (fcw7_r1 ),
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.fcw8 (fcw8_r1 ),
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.fcw9 (fcw9_r1 ),
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.fcw10 (fcw10_r1 ),
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.fcw11 (fcw11_r1 ),
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.fcw12 (fcw12_r1 ),
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.fcw13 (fcw13_r1 ),
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.fcw14 (fcw14_r1 ),
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.fcw15 (fcw15_r1 ),
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.fcw16 (fcw16_r1 ),
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.cos_0 (cos_0 ),
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.cos_1 (cos_1 ),
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.cos_2 (cos_2 ),
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.cos_3 (cos_3 ),
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.cos_4 (cos_4 ),
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.cos_5 (cos_5 ),
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.cos_6 (cos_6 ),
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.cos_7 (cos_7 ),
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.cos_8 (cos_8 ),
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.cos_9 (cos_9 ),
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.cos_10 (cos_10 ),
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.cos_11 (cos_11 ),
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.cos_12 (cos_12 ),
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.cos_13 (cos_13 ),
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.cos_14 (cos_14 ),
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.cos_15 (cos_15 ),
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.sin_0 (sin_0 ),
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.sin_1 (sin_1 ),
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.sin_2 (sin_2 ),
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.sin_3 (sin_3 ),
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.sin_4 (sin_4 ),
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.sin_5 (sin_5 ),
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.sin_6 (sin_6 ),
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.sin_7 (sin_7 ),
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.sin_8 (sin_8 ),
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.sin_9 (sin_9 ),
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.sin_10 (sin_10 ),
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.sin_11 (sin_11 ),
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.sin_12 (sin_12 ),
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.sin_13 (sin_13 ),
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.sin_14 (sin_14 ),
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.sin_15 (sin_15 )
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);
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endmodule
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