337 lines
11 KiB
Verilog
337 lines
11 KiB
Verilog
// Relese History
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// Version Date Author Description
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// 1.1 2024-04-08 ZYZ
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords : 1.add Env_vld
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// 2.add Mod_vld
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// 3.change the use of Mod_enable
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// 4.divide modem into FM and AM
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//
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//
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//
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module freqmod (
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//System Signal
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input Dig_Clk //Module Clock
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,input Dig_Resetn //Module Reset Signal
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//Envelope Data
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,input signed [15:0] Env_Idata //env_i is signed (two's complement)
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,input signed [15:0] Env_Qdata //env_q is signed (two's complement)
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,input Env_Vld //env data is vld
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//Nco data
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,input signed [15:0] Nco_Sin //nco_sin is signed (two's complement)
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,input signed [15:0] Nco_Cos //nco_cos is signed (two's complement)
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//Config Signal
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,input Mod_Sideband_Sel //1'b0: Mod_data_i = Icoswd+Qsinwd, Mod_data_q = -Isinwd+Qcoswd
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//1'b1: Mod_data_i = Icoswd-Qsinwd, Mod_data_q = Isinwd+Qcoswd
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,input Mod_Enable //1'b0: disable Modem,1'b1:enable modem
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//Output modem data
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,output signed [15:0] Mod_Data_I //Modem output data for I
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,output signed [15:0] Mod_Data_Q //Modem output data for Q
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,output Mod_Vld //Modem output data vld
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);
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//////////////////////////////////////////////////////////////
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// Wire & reg
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//////////////////////////////////////////////////////////////
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//The temporary result Regs of a multiplication operation.
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wire signed [31:0] mult_isin_tmp;
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wire signed [31:0] mult_icos_tmp;
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wire signed [31:0] mult_qsin_tmp;
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wire signed [31:0] mult_qcos_tmp;
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//The processing of a multiplication result.
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wire signed [15:0] mult_isin_w;
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wire signed [15:0] mult_icos_w;
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wire signed [15:0] mult_qsin_w;
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wire signed [15:0] mult_qcos_w;
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//The multiplier processing result register.
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reg signed [15:0] mult_isin_r;
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reg signed [15:0] mult_icos_r;
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reg signed [15:0] mult_qsin_r;
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reg signed [15:0] mult_qcos_r;
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//Temporary storage of IQ data.
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wire signed [16:0] adder0_icosqsin_tmp;
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wire signed [16:0] adder1_isinqcos_tmp;
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//Output of IQ data stored in registers.
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reg signed [15:0] adder0_icosqsin_r;
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reg signed [15:0] adder1_isinqcos_r;
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//Modulation data valid flag Regs.
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reg [7 :0] freqmod_data_vld_dly;
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//shifting register,Env_Idata
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reg signed [15:0] Env_Idata_r1;
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reg signed [15:0] Env_Idata_r2;
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reg signed [15:0] Env_Idata_r3;
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reg signed [15:0] Env_Idata_r4;
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(!Dig_Resetn)
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begin
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Env_Idata_r1 <= 16'b0;
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Env_Idata_r2 <= 16'b0;
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Env_Idata_r3 <= 16'b0;
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Env_Idata_r4 <= 16'b0;
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end
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else if(~Mod_Enable)
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begin
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Env_Idata_r1 <= 16'b0;
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Env_Idata_r2 <= Env_Idata_r1;
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Env_Idata_r3 <= Env_Idata_r2;
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Env_Idata_r4 <= Env_Idata_r3;
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end
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else begin
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Env_Idata_r1 <= Env_Idata;
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Env_Idata_r2 <= Env_Idata_r1;
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Env_Idata_r3 <= Env_Idata_r2;
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Env_Idata_r4 <= Env_Idata_r3;
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end
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end
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//shifting register,Env_Qdata
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reg signed [15:0] Env_Qdata_r1;
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reg signed [15:0] Env_Qdata_r2;
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reg signed [15:0] Env_Qdata_r3;
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reg signed [15:0] Env_Qdata_r4;
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(!Dig_Resetn)
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begin
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Env_Qdata_r1 <= 16'b0;
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Env_Qdata_r2 <= 16'b0;
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Env_Qdata_r3 <= 16'b0;
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Env_Qdata_r4 <= 16'b0;
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end
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else if(~Mod_Enable)
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begin
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Env_Qdata_r1 <= 16'b0;
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Env_Qdata_r2 <= Env_Qdata_r1;
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Env_Qdata_r3 <= Env_Qdata_r2;
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Env_Qdata_r4 <= Env_Qdata_r3;
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end
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else begin
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Env_Qdata_r1 <= Env_Qdata;
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Env_Qdata_r2 <= Env_Qdata_r1;
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Env_Qdata_r3 <= Env_Qdata_r2;
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Env_Qdata_r4 <= Env_Qdata_r3;
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end
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end
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//////////////////////////////////////////////////////////////
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// Orthogonal modulation
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//////////////////////////////////////////////////////////////
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//DW_mult_pipe Instantiation -> Env_Idata * Nco_Sin
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DW_mult_pipe #(
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.a_width ( 16 )
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,.b_width ( 16 )
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,.num_stages ( 3 )
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,.stall_mode ( 0 )
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,.rst_mode ( 1 )
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,.op_iso_mode ( 0 )
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) inst_isin_mult (
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.clk ( Dig_Clk )
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,.rst_n ( Dig_Resetn )
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,.en ( 1'b1 )
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,.a ( Env_Idata_r4 )
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,.b ( Nco_Sin )
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,.tc ( 1'b1 )
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,.product ( mult_isin_tmp )
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);
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//DW_mult_pipe Instantiation -> Env_Idata * Nco_Cos
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DW_mult_pipe #(
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.a_width ( 16 )
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,.b_width ( 16 )
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,.num_stages ( 3 )
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,.stall_mode ( 0 )
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,.rst_mode ( 1 )
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,.op_iso_mode ( 0 )
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) inst_icos_mult (
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.clk ( Dig_Clk )
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,.rst_n ( Dig_Resetn )
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,.en ( 1'b1 )
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,.a ( Env_Idata_r4 )
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,.b ( Nco_Cos )
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,.tc ( 1'b1 )
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,.product ( mult_icos_tmp )
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);
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//DW_mult_pipe Instantiation -> Env_Qdata * Nco_Sin
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DW_mult_pipe #(
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.a_width ( 16 )
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,.b_width ( 16 )
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,.num_stages ( 3 )
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,.stall_mode ( 0 )
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,.rst_mode ( 1 )
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,.op_iso_mode ( 0 )
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) inst_qsin_mult (
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.clk ( Dig_Clk )
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,.rst_n ( Dig_Resetn )
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,.en ( 1'b1 )
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,.a ( Env_Qdata_r4 )
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,.b ( Nco_Sin )
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,.tc ( 1'b1 )
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,.product ( mult_qsin_tmp )
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);
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//DW_mult_pipe Instantiation -> Env_Qdata * Nco_Cos
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DW_mult_pipe #(
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.a_width ( 16 )
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,.b_width ( 16 )
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,.num_stages ( 3 )
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,.stall_mode ( 0 )
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,.rst_mode ( 1 )
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,.op_iso_mode ( 0 )
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) inst_qcos_mult (
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.clk ( Dig_Clk )
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,.rst_n ( Dig_Resetn )
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,.en ( 1'b1 )
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,.a ( Env_Qdata_r4 )
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,.b ( Nco_Cos )
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,.tc ( 1'b1 )
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,.product ( mult_qcos_tmp )
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);
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//////////////////////////////////////////////////////////////
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// The processing of a multiplication result.
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//////////////////////////////////////////////////////////////
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assign mult_isin_w = {mult_isin_tmp[31],mult_isin_tmp[29:15]} +mult_isin_tmp[14];
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assign mult_icos_w = {mult_icos_tmp[31],mult_icos_tmp[29:15]} +mult_icos_tmp[14];
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assign mult_qsin_w = {mult_qsin_tmp[31],mult_qsin_tmp[29:15]} +mult_qsin_tmp[14];
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assign mult_qcos_w = {mult_qcos_tmp[31],mult_qcos_tmp[29:15]} +mult_qcos_tmp[14];
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//////////////////////////////////////////////////////////////
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// The multiplier processing result register.
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//////////////////////////////////////////////////////////////
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//mult_isin_r
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(Dig_Resetn == 1'b0) begin
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mult_isin_r <= 16'd0;
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end
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else begin
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mult_isin_r <= mult_isin_w;
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end
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end
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//mult_icos_r
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(Dig_Resetn == 1'b0) begin
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mult_icos_r <= 16'd0;
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end
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else begin
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mult_icos_r <= mult_icos_w;
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end
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end
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//mult_qsin_r
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(Dig_Resetn == 1'b0) begin
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mult_qsin_r <= 16'd0;
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end
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else begin
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mult_qsin_r <= mult_qsin_w;
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end
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end
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//mult_qcos_r
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(Dig_Resetn == 1'b0) begin
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mult_qcos_r <= 16'd0;
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end
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else begin
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mult_qcos_r <= mult_qcos_w;
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end
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end
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//////////////////////////////////////////////////////////////
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// Orthogonal modulation
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//////////////////////////////////////////////////////////////
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assign adder0_icosqsin_tmp = ~Mod_Sideband_Sel ? (mult_icos_r + mult_qsin_r):(mult_icos_r - mult_qsin_r);
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//1'b0: adder0_icosqsin_tmp = Icoswd+Qsinwd, 1'b1:adder0_icosqsin_tmp = Icoswd-Qsinwd
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assign adder1_isinqcos_tmp = Mod_Sideband_Sel ? (mult_isin_r + mult_qcos_r):(-mult_isin_r + mult_qcos_r);
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//1'b0: adder1_isinqcos_tmp = Isinwd+Qcoswd, 1'b1:adder1_isinqcos_tmp = -Isinwd+Qcoswd
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//////////////////////////////////////////////////////////////
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// Output of IQ data stored in registers.
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//////////////////////////////////////////////////////////////
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(Dig_Resetn == 1'b0) begin
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adder0_icosqsin_r <= 16'd0;
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end
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else if(adder0_icosqsin_tmp[16:15] == 2'b01)begin
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adder0_icosqsin_r <= 32767;
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end
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else if (adder0_icosqsin_tmp[16:15] == 2'b10)begin
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adder0_icosqsin_r <= -32768;
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end
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else begin
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adder0_icosqsin_r <= {adder0_icosqsin_tmp[16],adder0_icosqsin_tmp[14:0]};
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end
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end
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(Dig_Resetn == 1'b0) begin
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adder1_isinqcos_r <= 16'd0;
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end
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else if (adder1_isinqcos_tmp[16:15] == 2'b01)begin
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adder1_isinqcos_r <= 32767;
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end
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else if (adder1_isinqcos_tmp[16:15] == 2'b10)begin
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adder1_isinqcos_r <= -32768;
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end
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else begin
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adder1_isinqcos_r <= {adder1_isinqcos_tmp[16],adder1_isinqcos_tmp[14:0]};
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end
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end
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assign Mod_Data_I = adder0_icosqsin_r;
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assign Mod_Data_Q = adder1_isinqcos_r;
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//////////////////////////////////////////////////////////////
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// Generation of Mod_Vld signal.
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//////////////////////////////////////////////////////////////
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//mod_data_vld_dly
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always @(posedge Dig_Clk or negedge Dig_Resetn) begin
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if(Dig_Resetn == 1'b0) begin
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freqmod_data_vld_dly <= 8'b0;
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end
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else begin
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freqmod_data_vld_dly <= {freqmod_data_vld_dly[6:0], Mod_Enable & Env_Vld};
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end
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end
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assign Mod_Vld = freqmod_data_vld_dly[7];
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endmodule
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