67 lines
3.2 KiB
Verilog
67 lines
3.2 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : v.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY AWG output data bais set
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module baisset (
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//System Signal
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input Dig_Clk //Module Clock
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,input Dig_Resetn //Module Reset Signal
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//FM Data_in
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,input [15:0] Bais_Data_I_i //Bais_data_I
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,input [15:0] Bais_Data_Q_i //Bais_data_Q
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,input Bais_Vld_i //Bais_data is valid
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//AM
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,input [15:0] Bais //Bais
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,input Bais_Enable //1'b0: disable Bais,1'b1:enable Bais
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//Output Bais data
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,output [15:0] Bais_Data_I_o //Bais output data for I
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,output [15:0] Bais_Data_Q_o //Bais output data for Q
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,output Bais_Vld_o //Bais output data vld
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,output Bais_I_Ov
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,output Bais_Q_Ov
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);
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wire [17:0] temp_data_i = Bais_Enable ? {{2{Bais_Data_I_i[15]}},Bais_Data_I_i} + {{2{Bais[15]}},Bais} : {{2{Bais_Data_I_i[15]}},Bais_Data_I_i};
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wire [17:0] temp_data_q = Bais_Enable ? {{2{Bais_Data_Q_i[15]}},Bais_Data_Q_i} + {{2{Bais[15]}},Bais} : {{2{Bais_Data_Q_i[15]}},Bais_Data_Q_i};
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//output data
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sirv_gnrl_dffr #(16) Bais_Data_I_o_dffr (temp_data_i[15:0], Bais_Data_I_o, Dig_Clk, Dig_Resetn);
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sirv_gnrl_dffr #(16) Bais_Data_Q_o_dffr (temp_data_q[15:0], Bais_Data_Q_o, Dig_Clk, Dig_Resetn);
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//output vld
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sirv_gnrl_dffr #(1) Bais_Vld_o_dffr (Bais_Vld_i, Bais_Vld_o, Dig_Clk, Dig_Resetn);
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//output overflow flag
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sirv_gnrl_dfflr #(1) Bais_I_Ov_dfflr (Bais_Vld_i, temp_data_i[17] ^ temp_data_i[16], Bais_I_Ov, Dig_Clk, Dig_Resetn);
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sirv_gnrl_dfflr #(1) Bais_Q_Ov_dfflr (Bais_Vld_i, temp_data_q[17] ^ temp_data_q[16], Bais_Q_Ov, Dig_Clk, Dig_Resetn);
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endmodule |