216 lines
15 KiB
Verilog
216 lines
15 KiB
Verilog
|
|
|
|
module tsmc_dpram #(
|
|
parameter DATAWIDTH = 32
|
|
,parameter ADDRWIDTH = 14
|
|
)(
|
|
input PortClk
|
|
,input [ADDRWIDTH-1 :0] PortAAddr
|
|
,input [DATAWIDTH-1 :0] PortADataIn
|
|
,input PortAWriteEnable //active low
|
|
,input PortAChipEnable //active low
|
|
,input [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable //active low
|
|
,output [DATAWIDTH-1 :0] PortADataOut
|
|
|
|
,input [ADDRWIDTH-1 :0] PortBAddr
|
|
,input [DATAWIDTH-1 :0] PortBDataIn
|
|
,input PortBWriteEnable //active low
|
|
,input PortBChipEnable //active low
|
|
,input [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable //active low
|
|
,output [DATAWIDTH-1 :0] PortBDataOut
|
|
);
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//Function
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
function integer clog2(input integer bit_depth);
|
|
begin
|
|
for(clog2=0;bit_depth>0;clog2=clog2+1)
|
|
bit_depth =bit_depth>>1;
|
|
end
|
|
endfunction
|
|
|
|
localparam LSB = clog2(DATAWIDTH/8 -1);
|
|
|
|
generate
|
|
if((DATAWIDTH == 32) && (ADDRWIDTH == 15)) begin:dpram_32X4096_generation
|
|
|
|
wire [DATAWIDTH-1:0] BWEBA;
|
|
wire [DATAWIDTH-1:0] BWEBB;
|
|
|
|
assign BWEBA = {{8{PortAByteWriteEnable[3]}},{8{PortAByteWriteEnable[2]}},{8{PortAByteWriteEnable[1]}},{8{PortAByteWriteEnable[0]}}};
|
|
assign BWEBB = {{8{PortBByteWriteEnable[3]}},{8{PortBByteWriteEnable[2]}},{8{PortBByteWriteEnable[1]}},{8{PortBByteWriteEnable[0]}}};
|
|
|
|
wire U0_CEBA;
|
|
wire U0_CEBB;
|
|
wire U1_CEBA;
|
|
wire U1_CEBB;
|
|
|
|
assign U0_CEBA = PortAAddr[ADDRWIDTH-1] | PortAChipEnable;
|
|
assign U0_CEBB = PortBAddr[ADDRWIDTH-1] | PortBChipEnable;
|
|
|
|
assign U1_CEBA = ~PortAAddr[ADDRWIDTH-1] | PortAChipEnable;
|
|
assign U1_CEBB = ~PortBAddr[ADDRWIDTH-1] | PortBChipEnable;
|
|
|
|
wire [DATAWIDTH-1:0] U0_QA;
|
|
wire [DATAWIDTH-1:0] U0_QB;
|
|
wire [DATAWIDTH-1:0] U1_QA;
|
|
wire [DATAWIDTH-1:0] U1_QB;
|
|
|
|
reg AA_1D_MSB;
|
|
reg AB_1D_MSB;
|
|
|
|
always @(posedge PortClk) begin
|
|
if(PortAWriteEnable == 1'b1) begin
|
|
AA_1D_MSB <= PortAAddr[ADDRWIDTH-1];
|
|
end
|
|
else begin
|
|
AA_1D_MSB <= AA_1D_MSB;
|
|
end
|
|
end
|
|
|
|
always @(posedge PortClk) begin
|
|
if(PortBWriteEnable == 1'b1) begin
|
|
AB_1D_MSB <= PortBAddr[ADDRWIDTH-1];
|
|
end
|
|
else begin
|
|
AB_1D_MSB <= AB_1D_MSB;
|
|
end
|
|
end
|
|
|
|
|
|
assign PortADataOut = {DATAWIDTH{~AA_1D_MSB}} & U0_QA
|
|
| {DATAWIDTH{AA_1D_MSB}} & U1_QA;
|
|
|
|
|
|
assign PortBDataOut = {DATAWIDTH{~AB_1D_MSB}} & U0_QB
|
|
| {DATAWIDTH{AB_1D_MSB}} & U1_QB;
|
|
tsdn28hpcpuhdb4096x32m4mw_170a U0_TSDN28HPCPUHDB4096X32M4MW (
|
|
.CLK ( PortClk )
|
|
,.CEBA ( U0_CEBA )
|
|
,.WEBA ( PortAWriteEnable )
|
|
,.BWEBA ( BWEBA )
|
|
,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
|
|
,.DA ( PortADataIn )
|
|
,.QA ( U0_QA )
|
|
,.CEBB ( U0_CEBB )
|
|
,.WEBB ( PortBWriteEnable )
|
|
,.BWEBB ( BWEBB )
|
|
,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
|
|
,.DB ( PortBDataIn )
|
|
,.QB ( U0_QB )
|
|
,.RTSEL ( 2'b00 )
|
|
,.WTSEL ( 2'b00 )
|
|
,.PTSEL ( 2'b00 )
|
|
);
|
|
|
|
tsdn28hpcpuhdb4096x32m4mw_170a U1_TSDN28HPCPUHDB4096X32M4MW (
|
|
.CLK ( PortClk )
|
|
,.CEBA ( U1_CEBA )
|
|
,.WEBA ( PortAWriteEnable )
|
|
,.BWEBA ( BWEBA )
|
|
,.AA ( PortAAddr[ADDRWIDTH-2:LSB] )
|
|
,.DA ( PortADataIn )
|
|
,.QA ( U1_QA )
|
|
,.CEBB ( U1_CEBB )
|
|
,.WEBB ( PortBWriteEnable )
|
|
,.BWEBB ( BWEBB )
|
|
,.AB ( PortBAddr[ADDRWIDTH-2:LSB] )
|
|
,.DB ( PortBDataIn )
|
|
,.QB ( U1_QB )
|
|
,.RTSEL ( 2'b00 )
|
|
,.WTSEL ( 2'b00 )
|
|
,.PTSEL ( 2'b00 )
|
|
);
|
|
end
|
|
|
|
else if((DATAWIDTH == 32) && (ADDRWIDTH == 8)) begin:spram_32X64_generation
|
|
wire [DATAWIDTH-1:0] BWEBA = {{8{PortAByteWriteEnable[3]}},{8{PortAByteWriteEnable[2]}},{8{PortAByteWriteEnable[1]}},{8{PortAByteWriteEnable[0]}}};
|
|
wire [DATAWIDTH-1:0] BWEBB = {{8{PortBByteWriteEnable[3]}},{8{PortBByteWriteEnable[2]}},{8{PortBByteWriteEnable[1]}},{8{PortBByteWriteEnable[0]}}};
|
|
tsdn28hpcpuhdb64x32m4mw_170a U_tsdn28hpcpuhdb64x32m4mw_170a (
|
|
.CLK ( PortClk )
|
|
,.CEBA ( PortAChipEnable )
|
|
,.WEBA ( PortAWriteEnable )
|
|
,.BWEBA ( BWEBA )
|
|
,.AA ( PortAAddr[ADDRWIDTH-1:LSB] )
|
|
,.DA ( PortADataIn )
|
|
,.QA ( PortADataOut )
|
|
,.CEBB ( PortBChipEnable )
|
|
,.WEBB ( PortBWriteEnable )
|
|
,.BWEBB ( BWEBB )
|
|
,.AB ( PortBAddr[ADDRWIDTH-1:LSB] )
|
|
,.DB ( PortBDataIn )
|
|
,.QB ( PortBDataOut )
|
|
,.RTSEL ( 2'b00 )
|
|
,.WTSEL ( 2'b00 )
|
|
,.PTSEL ( 2'b00 )
|
|
);
|
|
end
|
|
else if((DATAWIDTH == 256) && (ADDRWIDTH == 12)) begin:spram_512X128_generation
|
|
genvar i;
|
|
wire [DATAWIDTH-1:0] BWEBA ;
|
|
wire [DATAWIDTH-1:0] BWEBB ;
|
|
for(i=0;i<DATAWIDTH/8;i=i+1) begin
|
|
assign BWEBA[8*i+:8] = {8{PortAByteWriteEnable[i]}};
|
|
assign BWEBB[8*i+:8] = {8{PortBByteWriteEnable[i]}};
|
|
end
|
|
tsdn28hpcpuhdb128x128m4mw_170a U0_tsdn28hpcpuhdb128x128m4mw_170a (
|
|
.CLK ( PortClk )
|
|
,.CEBA ( PortAChipEnable )
|
|
,.WEBA ( PortAWriteEnable )
|
|
,.BWEBA ( BWEBA[127:0] )
|
|
,.AA ( PortAAddr[ADDRWIDTH-1:LSB] )
|
|
,.DA ( PortADataIn[127:0] )
|
|
,.QA ( PortADataOut[127:0] )
|
|
,.CEBB ( PortBChipEnable )
|
|
,.WEBB ( PortBWriteEnable )
|
|
,.BWEBB ( BWEBB[127:0] )
|
|
,.AB ( PortBAddr[ADDRWIDTH-1:LSB] )
|
|
,.DB ( PortBDataIn[127:0] )
|
|
,.QB ( PortBDataOut[127:0] )
|
|
,.RTSEL ( 2'b00 )
|
|
,.WTSEL ( 2'b00 )
|
|
,.PTSEL ( 2'b00 )
|
|
);
|
|
tsdn28hpcpuhdb128x128m4mw_170a U1_tsdn28hpcpuhdb128x128m4mw_170a (
|
|
.CLK ( PortClk )
|
|
,.CEBA ( PortAChipEnable )
|
|
,.WEBA ( PortAWriteEnable )
|
|
,.BWEBA ( BWEBA[255:128] )
|
|
,.AA ( PortAAddr[ADDRWIDTH-1:LSB] )
|
|
,.DA ( PortADataIn[255:128] )
|
|
,.QA ( PortADataOut[255:128] )
|
|
,.CEBB ( PortBChipEnable )
|
|
,.WEBB ( PortBWriteEnable )
|
|
,.BWEBB ( BWEBB[255:128] )
|
|
,.AB ( PortBAddr[ADDRWIDTH-1:LSB] )
|
|
,.DB ( PortBDataIn[255:128] )
|
|
,.QB ( PortBDataOut[255:128] )
|
|
,.RTSEL ( 2'b00 )
|
|
,.WTSEL ( 2'b00 )
|
|
,.PTSEL ( 2'b00 )
|
|
);
|
|
|
|
end
|
|
else begin:dpram_model_generation
|
|
dpram_model #(
|
|
.DATAWIDTH ( DATAWIDTH )
|
|
,.ADDRWIDTH ( ADDRWIDTH-LSB )
|
|
) U_dpram_model (
|
|
.PortClk ( PortClk )
|
|
,.PortAWriteEnable ( PortAWriteEnable )
|
|
,.PortAChipEnable ( PortAChipEnable )
|
|
,.PortAByteWriteEnable ( PortAByteWriteEnable )
|
|
,.PortAAddr ( PortAAddr[ADDRWIDTH-1:LSB] )
|
|
,.PortADataIn ( PortADataIn )
|
|
,.PortADataOut ( PortADataOut )
|
|
,.PortBWriteEnable ( PortBWriteEnable )
|
|
,.PortBChipEnable ( PortBChipEnable )
|
|
,.PortBByteWriteEnable ( PortBByteWriteEnable )
|
|
,.PortBAddr ( PortBAddr[ADDRWIDTH-1:LSB] )
|
|
,.PortBDataIn ( PortBDataIn )
|
|
,.PortBDataOut ( PortBDataOut )
|
|
);
|
|
end
|
|
endgenerate
|
|
endmodule
|