101 lines
3.7 KiB
Verilog
101 lines
3.7 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : ssram_model.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 1.0 2022-08-25 PWY
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module dpram_model #(
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parameter DATAWIDTH = 32
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,parameter ADDRWIDTH = 13
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)(
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input PortClk
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,input [(ADDRWIDTH-1) :0] PortAAddr
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,input [(DATAWIDTH-1) :0] PortADataIn
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,input PortAWriteEnable
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,input PortAChipEnable //active low
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,input [(DATAWIDTH/8)-1:0] PortAByteWriteEnable
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,output reg [(DATAWIDTH-1) :0] PortADataOut
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,input [(ADDRWIDTH-1) :0] PortBAddr
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,input [(DATAWIDTH-1) :0] PortBDataIn
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,input PortBWriteEnable
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,input PortBChipEnable //active low
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,input [(DATAWIDTH/8)-1:0] PortBByteWriteEnable
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,output reg [(DATAWIDTH-1) :0] PortBDataOut
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);
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////////////////////////////////////////////////////////////////////////////////
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//Function
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////////////////////////////////////////////////////////////////////////////////
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function integer clog2(input integer bit_depth);
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begin
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for(clog2=0;bit_depth>0;clog2=clog2+1)
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bit_depth =bit_depth>>1;
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end
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endfunction
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localparam LSB = clog2(DATAWIDTH/8 -1);
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localparam NUM = DATAWIDTH/8;
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localparam MEMDEPTH = 2**(ADDRWIDTH-LSB);
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generate
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genvar i;
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for(i=0;i<NUM;i=i+1) begin :dpram_model
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reg [7:0] mem [(MEMDEPTH-1):0] /* synthesis syn_ramstyle = "no_rw_check" */;
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always @(posedge PortClk) begin
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if(!PortAWriteEnable && !PortAByteWriteEnable[i] && !PortAChipEnable) begin
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mem[PortAAddr] <= PortADataIn[8*(i+1)-1-:8];
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//PortADataOut[8*(i+1)-1-:8] <= PortADataIn[8*(i+1)-1-:8];
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end
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end
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always @(posedge PortClk) begin
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if(!PortBWriteEnable && !PortBByteWriteEnable[i] && !PortBChipEnable) begin
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mem[PortBAddr] <= PortBDataIn[8*(i+1)-1-:8];
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//PortADataOut[8*(i+1)-1-:8] <= PortADataIn[8*(i+1)-1-:8];
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end
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end
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always @(posedge PortClk) begin
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PortADataOut[8*(i+1)-1-:8] <= mem[PortAAddr[ADDRWIDTH-1:0]];
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end
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always @(posedge PortClk) begin
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PortBDataOut[8*(i+1)-1-:8] <= mem[PortBAddr[ADDRWIDTH-1:0]];
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end
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end
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endgenerate
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endmodule
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