693 lines
28 KiB
Verilog
693 lines
28 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/03/19 10:41:08
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// Design Name:
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// Module Name: intpll_regfile
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// -----------------------------------------------------------
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// -- Register address offset macros
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// -----------------------------------------------------------
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//Int pll Ctrl Register
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`define INTPLL_REFCTRL 8'h00
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`define INTPLL_PCNT 8'h04
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`define INTPLL_PFDCTRL 8'h08
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`define INTPLL_SPDCTRL 8'h0C
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`define INTPLL_PTATCTRL 8'h10
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`define INTPLL_FLLCTRL 8'h14
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`define INTPLL_SELCTRL 8'h18
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`define INTPLL_VCOCTRL 8'h1C
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`define INTPLL_VCOFBADJ 8'h20
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`define INTPLL_AFCCTRL 8'h24
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`define INTPLL_AFCCNT 8'h28
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`define INTPLL_AFCLDCNT 8'h2C
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`define INTPLL_AFCPRES 8'h30
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`define INTPLL_AFCLDTCC 8'h34
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`define INTPLL_AFCFBTCC 8'h38
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`define INTPLL_DIVCFG 8'h3C
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`define INTPLL_TCLKCFG 8'h40
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`define INTPLL_DCLKSEL 8'h44
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`define INTPLL_STATUS 8'h48
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`define INTPLL_SYNCFG 8'h4C
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`define INTPLL_UPDATE 8'h50
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`define INTPLL_CLKRXPD 8'h54
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module intpll_regfile (
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//system port
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input clk // System Main Clock
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,input rst_n // Spi Reset active low
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//rw op port
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,input [31 :0] wrdata // write data
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,input wren // write enable
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,input [7 :0] rwaddr // read & write address
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,input rden // read enable
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,output [31 :0] rddata // read data
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,output ref_sel // Clock source selection for a frequency divider;
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// 1'b0:External clock source
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// 1'b1:internal phase-locked loop clock source
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,output ref_en // Input reference clock enable
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// 1'b0:enable,1'b1:disable
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,output ref_s2d_en // Referenced clock differential to single-ended conversion enable
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// 1'b0:enable,1'b1:disable
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,output [6 :0] p_cnt // P counter
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,output pfd_delay // PFD Dead Zone
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,output pfd_dff_Set // Setting the PFD register,active high
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,output pfd_dff_4and // PFD output polarity
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,output [3 :0] spd_div // SPD Frequency Divider
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,output spd_pulse_width // Pulse Width of SPD
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,output spd_pulse_sw // Pulse sw of SPD
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,output cpc_sel // current source selection
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,output [1 :0] swcp_i // PTAT current switch
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,output [3 :0] sw_ptat_r // PTAT current adjustment
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,output [1 :0] sw_fll_cpi // Phase-locked loop charge pump current
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,output sw_fll_delay // PLL Dead Zone
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,output pfd_sel // PFD Loop selection
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,output spd_sel // SPD Loop selection
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,output fll_sel // FLL Loop selection
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,output vco_tc // VCO temperature compensation
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,output vco_tcr // VCO temperature compensation resistor
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,output vco_gain_adj // VCO gain adjustment
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,output vco_gain_adj_r // VCO gain adjustment resistor
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,output [2 :0] vco_cur_adj // VCO current adjustment
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,output vco_buff_en // VCO buff enable,active high
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,output vco_en // VCO enable,active high
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,output [2 :0] pll_dpwr_adj // PLL frequency division output power adjustment
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,output [6 :0] vco_fb_adj // VCO frequency band adjustment
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,output afc_en // AFC enable
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,output afc_shutdown // AFC module shutdown signal
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,output [0 :0] afc_det_speed // AFC detection speed
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,output [0 :0] flag_out_sel // Read and choose the signs
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,output afc_reset // AFC reset
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,output [10 :0] afc_cnt // AFC frequency band adjustment function counter
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// counting time adjustment
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,output [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection
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// feature counter
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,output [3 :0] afc_pres // Adjusting the resolution of the AFC comparator
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,output [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count
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,output [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band
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// adjustment function
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,output [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
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,output [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
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,output [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable
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,output [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
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,output [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable
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,output sync_oe // SYNC signal output enable, hign active
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,output clkrx_pdn // Clock Rx Power down, Ative Low
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,input pll_lock // PLL LOCK
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);
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localparam L = 1'b0,
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H = 1'b1;
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// ------------------------------------------------------
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// -- Register enable (select) wires
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// ------------------------------------------------------
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wire refctrlen ;
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wire pcnten ;
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wire pfdctrlen ;
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wire spdctrlen ;
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wire ptatctrlen ;
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wire fllctrlen ;
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wire selctrlen ;
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wire vcoctrlen ;
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wire vcofbadjen ;
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wire afcctrlen ;
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wire afccnten ;
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wire afcldcnten ;
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wire afcpresen ;
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wire afcldtccen ;
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wire afcfbtccen ;
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wire divcfgen ;
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wire tclkcfgen ;
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wire dclkselen ;
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wire statusen ;
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wire synccfgen ;
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wire updateen ;
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wire clkrxpden ;
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// ------------------------------------------------------
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// -- Register write enable wires
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// ------------------------------------------------------
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wire refctrlwe ;
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wire pcntwe ;
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wire pfdctrlwe ;
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wire spdctrlwe ;
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wire ptatctrlwe ;
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wire fllctrlwe ;
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wire selctrlwe ;
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wire vcoctrlwe ;
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wire vcofbadjwe ;
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wire afcctrlwe ;
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wire afccntwe ;
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wire afcldcntwe ;
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wire afcpreswe ;
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wire afcldtccwe ;
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wire afcfbtccwe ;
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wire divcfgwe ;
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wire tclkcfgwe ;
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wire dclkselwe ;
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wire synccfgwe ;
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wire updatewe ;
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wire clkrxpdwe ;
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// ------------------------------------------------------
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// -- Misc Registers
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// ------------------------------------------------------
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wire [2 :0] refctrl_r ;
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wire [6 :0] pcnt_r ;
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wire [2 :0] pfdctrl_r ;
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wire [5 :0] spdctrl_r ;
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wire [6 :0] ptatctrl_r ;
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wire [2 :0] fllctrl_r ;
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wire [2 :0] selctrl_r ;
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wire [11:0] vcoctrl_r ;
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wire [6 :0] vcofbadj_r ;
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wire [4 :0] afcctrl_r ;
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wire [10:0] afccnt_r ;
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wire [10:0] afcldcnt_r ;
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wire [3 :0] afcpres_r ;
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wire [14:0] afcldtcc_r ;
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wire [14:0] afcfbtcc_r ;
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wire [0 :0] divrstsel_r ;
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wire [2 :0] testclk_r ;
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wire [7 :0] digclksel_r ;
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wire [1 :0] sync_r ;
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wire clkrxpd_r ;
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wire [2 :0] refctrl_updr ;
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wire [6 :0] pcnt_updr ;
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wire [2 :0] pfdctrl_updr ;
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wire [5 :0] spdctrl_updr ;
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wire [6 :0] ptatctrl_updr ;
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wire [2 :0] fllctrl_updr ;
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wire [2 :0] selctrl_updr ;
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wire [11:0] vcoctrl_updr ;
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wire [6 :0] vcofbadj_updr ;
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wire [4 :0] afcctrl_updr ;
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wire [10:0] afccnt_updr ;
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wire [10:0] afcldcnt_updr ;
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wire [3 :0] afcpres_updr ;
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wire [14:0] afcldtcc_updr ;
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wire [14:0] afcfbtcc_updr ;
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reg [31 :0] rddata_reg ;
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// ------------------------------------------------------
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// -- Address decoder
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//
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// Decodes the register address offset input(reg_addr)
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// to produce enable (select) signals for each of the
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// SW-registers in the macrocell. The reg_addr input
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// is bits [15:0] of the paddr bus.
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// ------------------------------------------------------
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assign refctrlen = (rwaddr[7:2] == `INTPLL_REFCTRL >>2) ? 1'b1 : 1'b0;
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assign pcnten = (rwaddr[7:2] == `INTPLL_PCNT >>2) ? 1'b1 : 1'b0;
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assign pfdctrlen = (rwaddr[7:2] == `INTPLL_PFDCTRL >>2) ? 1'b1 : 1'b0;
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assign spdctrlen = (rwaddr[7:2] == `INTPLL_SPDCTRL >>2) ? 1'b1 : 1'b0;
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assign ptatctrlen = (rwaddr[7:2] == `INTPLL_PTATCTRL >>2) ? 1'b1 : 1'b0;
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assign fllctrlen = (rwaddr[7:2] == `INTPLL_FLLCTRL >>2) ? 1'b1 : 1'b0;
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assign selctrlen = (rwaddr[7:2] == `INTPLL_SELCTRL >>2) ? 1'b1 : 1'b0;
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assign vcoctrlen = (rwaddr[7:2] == `INTPLL_VCOCTRL >>2) ? 1'b1 : 1'b0;
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assign vcofbadjen = (rwaddr[7:2] == `INTPLL_VCOFBADJ >>2) ? 1'b1 : 1'b0;
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assign afcctrlen = (rwaddr[7:2] == `INTPLL_AFCCTRL >>2) ? 1'b1 : 1'b0;
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assign afccnten = (rwaddr[7:2] == `INTPLL_AFCCNT >>2) ? 1'b1 : 1'b0;
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assign afcldcnten = (rwaddr[7:2] == `INTPLL_AFCLDCNT >>2) ? 1'b1 : 1'b0;
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assign afcpresen = (rwaddr[7:2] == `INTPLL_AFCPRES >>2) ? 1'b1 : 1'b0;
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assign afcldtccen = (rwaddr[7:2] == `INTPLL_AFCLDTCC >>2) ? 1'b1 : 1'b0;
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assign afcfbtccen = (rwaddr[7:2] == `INTPLL_AFCFBTCC >>2) ? 1'b1 : 1'b0;
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assign divcfgen = (rwaddr[7:2] == `INTPLL_DIVCFG >>2) ? 1'b1 : 1'b0;
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assign tclkcfgen = (rwaddr[7:2] == `INTPLL_TCLKCFG >>2) ? 1'b1 : 1'b0;
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assign dclkselen = (rwaddr[7:2] == `INTPLL_DCLKSEL >>2) ? 1'b1 : 1'b0;
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assign statusen = (rwaddr[7:2] == `INTPLL_STATUS >>2) ? 1'b1 : 1'b0;
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assign synccfgen = (rwaddr[7:2] == `INTPLL_SYNCFG >>2) ? 1'b1 : 1'b0;
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assign updateen = (rwaddr[7:2] == `INTPLL_UPDATE >>2) ? 1'b1 : 1'b0;
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assign clkrxpden = (rwaddr[7:2] == `INTPLL_CLKRXPD >>2) ? 1'b1 : 1'b0;
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// ------------------------------------------------------
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// -- Write enable signals
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//
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// Write enable signals for writable SW-registers.
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// The write enable for each register is the ANDed
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// result of the register enable and the input reg_wren
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// ------------------------------------------------------
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assign refctrlwe = refctrlen & wren;
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assign pcntwe = pcnten & wren;
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assign pfdctrlwe = pfdctrlen & wren;
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assign spdctrlwe = spdctrlen & wren;
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assign ptatctrlwe = ptatctrlen & wren;
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assign fllctrlwe = fllctrlen & wren;
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assign selctrlwe = selctrlen & wren;
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assign vcoctrlwe = vcoctrlen & wren;
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assign vcofbadjwe = vcofbadjen & wren;
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assign afcctrlwe = afcctrlen & wren;
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assign afccntwe = afccnten & wren;
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assign afcldcntwe = afcldcnten & wren;
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assign afcpreswe = afcpresen & wren;
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assign afcldtccwe = afcldtccen & wren;
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assign afcfbtccwe = afcfbtccen & wren;
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assign divcfgwe = divcfgen & wren;
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assign tclkcfgwe = tclkcfgen & wren;
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assign dclkselwe = dclkselen & wren;
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assign synccfgwe = synccfgen & wren;
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assign updatewe = updateen & wren;
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assign clkrxpdwe = clkrxpden & wren;
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// ------------------------------------------------------
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// -- refctrl_r Register
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//
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// Write refctrl_r for 'REFCTRL' : 32-bit register
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// Register is split into the following bit fields
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//
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// [2] --> ref_s2d_en default : 1'b1
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// [1] --> ref_en default : 1'b1
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// [0] --> ref_sel default : 1'b0
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(3) refctrl_dfflrd (3'b110, refctrlwe, wrdata[2:0], refctrl_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(3) refctrl_updr_dfflrd (3'b110, updatewe, refctrl_r, refctrl_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- pcnt_r Register
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//
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// Write pcnt_r for 'PCNT' : 32-bit register
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// Register is split into the following bit fields
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//
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// [6 : 0] --> pcnt default : 7'b000_1100
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(7) pcnt_dfflrd (7'b000_1100, pcntwe, wrdata[6:0], pcnt_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(7) pcnt_updr_dfflrd (7'b000_1100, updatewe, pcnt_r, pcnt_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- pfdctrl_r Register
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//
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// Write pfdctrl_reg for 'REFCTRL' : 32-bit register
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// Register is split into the following bit fields
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//
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// [2] --> pfd_dff_4and default : 1'b1
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// [1] --> pfd_dff_Set default : 1'b1
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// [0] --> pfd_delay default : 1'b0
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(3) pfdctrl_dfflrd (3'b110, pfdctrlwe, wrdata[2:0], pfdctrl_r, clk, rst_n);//////////////////////////////////////////////
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//update
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sirv_gnrl_dfflrd #(3) pfdctrl_updr_dfflrd (3'b110, updatewe, pfdctrl_r, pfdctrl_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- spdctrl_r Register
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//
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// Write spdctrl_r for 'SPDCTRL' : 32-bit register
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// Register is split into the following bit fields
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//
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// [5 ] spd_pulse_sw default : 1'b0
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// [4 ] spd_pulse_width default : 1'b0
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// [3:0] spd_div default : 4'b0100
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(6) spdctrl_dfflrd (6'b00_0100, spdctrlwe, wrdata[5:0], spdctrl_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(6) spdctrl_updr_dfflrd (6'b00_0100, updatewe, spdctrl_r, spdctrl_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- ptatctrl_r Register
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//
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// Write ptatctrl_r for 'PTATCTRL' : 32-bit register
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// Register is split into the following bit fields
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//
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// [6 ] cpc_sel default : 1'b1
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// [5:4] swcp_i default : 2'b01
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// [3:0] sw_ptat_r default : 4'b1000
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(7) ptatctrl_dfflrd (7'b101_1000, ptatctrlwe, wrdata[6:0], ptatctrl_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(7) ptatctrl_updr_dfflrd (7'b101_1000, updatewe, ptatctrl_r, ptatctrl_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- fllctrl_r Register
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//
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// Write fllctrl_r for 'FLLCTRL' : 32-bit register
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// Register is split into the following bit fields
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//
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// [2 ] sw_fll_delay default : 1'b0
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// [1:0] sw_fll_cpi default : 2'b11
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(3) fllctrl_dfflrd (3'b011, fllctrlwe, wrdata[2:0], fllctrl_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(3) fllctrl_updr_dfflrd (3'b011, updatewe, fllctrl_r, fllctrl_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- selctrl_r Register
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//
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// Write selctrl_r for 'SELCTRL' : 32-bit register
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// Register is split into the following bit fields
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//
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// [2] fll_sel default : 1'b0
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// [1] spd_sel default : 1'b1
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// [0] pfd_sel default : 1'b0
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(3) selctrl_dfflrd (3'b010, selctrlwe, wrdata[2:0], selctrl_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(3) selctrl_updr_dfflrd (3'b010, updatewe, selctrl_r, selctrl_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- vcoctrl_r Register
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//
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// Write vcoctrl_r for 'VCOCTRL' : 32-bit register
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// Register is split into the following bit fields
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//
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// [11:9] pll_dpwr_adj default : 3'b111
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// [8 ] vco_en default : 1'b1
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// [7 ] vco_buff_en default : 1'b1
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// [6 :4] vco_cur_adj default : 3'b111
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// [3 ] vco_gain_adj_r default : 1'b0
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// [2 ] vco_gain_adj default : 1'b0
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// [1 ] vco_tcr default : 1'b0
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// [0 ] vco_tc default : 1'b0
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(12) vcoctrl_dfflrd (12'b1111_1111_0000, vcoctrlwe, wrdata[11:0], vcoctrl_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(12) vcoctrl_updr_dfflrd (12'b1111_1111_0000, updatewe, vcoctrl_r, vcoctrl_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- vcofbadj_r Register
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//
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|
// Write vcofbadj_r for 'VCOFBADJ' : 32-bit register
|
|
// Register is split into the following bit fields
|
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//
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// [6 : 0] --> vco_fb_adj default : 7'b000_0000
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|
// ------------------------------------------------------
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sirv_gnrl_dfflrd #(7) vcofbadj_dfflrd (7'b000_0000, vcofbadjwe, wrdata[6:0], vcofbadj_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(7) vcofbadj_updr_dfflrd (7'b000_0000, updatewe, vcofbadj_r, vcofbadj_updr, clk, rst_n);
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// ------------------------------------------------------
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|
// -- afcctrl_r Register
|
|
//
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|
// Write afcctrl_r for 'AFCCTRL' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
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// [4] afc_det_speed // default : 1'b0
|
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// [3] flag_out_sel // default : 1'b0
|
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// [2] afc_shutdown // default : 1'b0
|
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// [1] afc_reset // default : 1'b0
|
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// [0] afc_en // default : 1'b0
|
|
// ------------------------------------------------------
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sirv_gnrl_dfflrd #(5) afcctrl_dfflrd (5'b0_0000, afcctrlwe, wrdata[4:0], afcctrl_r, clk, rst_n);
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|
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//update
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sirv_gnrl_dfflrd #(5) afcctrl_updr_dfflrd (5'b0_0000, updatewe, afcctrl_r, afcctrl_updr, clk, rst_n);
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|
|
// ------------------------------------------------------
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|
// -- afccnt_r Register
|
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//
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|
// Write afccnt_r for 'AFCCnt' : 32-bit register
|
|
// Register is split into the following bit fields
|
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//
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// [10:0] --> afc_cnt default : 11'b000_1100_1000
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|
// ------------------------------------------------------
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|
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sirv_gnrl_dfflrd #(11) afccnt_dfflrd (11'b000_1100_1000, afccntwe, wrdata[10:0], afccnt_r, clk, rst_n);
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|
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//update
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sirv_gnrl_dfflrd #(11) afccnt_updr_dfflrd (11'b000_1100_1000, updatewe, afccnt_r, afccnt_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- afccnt_r Register
|
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//
|
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// Write afcldcnt_r for 'AFCLDCnt' : 32-bit register
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// Register is split into the following bit fields
|
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//
|
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// [10:0] --> afcld_cnt default : 11'b110_0100_0000
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(11) afcldcnt_dfflrd (11'b110_0100_0000, afcldcntwe, wrdata[10:0], afcldcnt_r, clk, rst_n);
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|
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//update
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sirv_gnrl_dfflrd #(11) afcldcnt_updr_dfflrd (11'b110_0100_0000, updatewe, afcldcnt_r, afcldcnt_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- afcpres_r Register
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|
//
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// Write afcpres_r for 'AFCPRES' : 32-bit register
|
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// Register is split into the following bit fields
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//
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// [3:0] --> afc_pres default : 4'b0011
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// ------------------------------------------------------
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sirv_gnrl_dfflrd #(4) afcpres_dfflrd (4'b0011, afcpreswe, wrdata[3:0], afcpres_r, clk, rst_n);
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//update
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sirv_gnrl_dfflrd #(4) afcpres_updr_dfflrd (4'b0011, updatewe, afcpres_r, afcpres_updr, clk, rst_n);
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// ------------------------------------------------------
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// -- afcldtcc_r Register
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//
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// Write afcldtcc_r for 'AFCLDTCC' : 32-bit register
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|
// Register is split into the following bit fields
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//
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// [14:0] --> afc_ld_tcc default : 15'b0
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|
// ------------------------------------------------------
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sirv_gnrl_dfflrd #(15) afcldtcc_dfflrd (15'b0, afcldtccwe, wrdata[14:0], afcldtcc_r, clk, rst_n);
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|
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//update
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sirv_gnrl_dfflrd #(15) afcldtcc_updr_dfflrd (15'b0, updatewe, afcldtcc_r, afcldtcc_updr, clk, rst_n);
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|
|
// ------------------------------------------------------
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// -- afcfbtcc_r Register
|
|
//
|
|
// Write afcfbtcc_r for 'AFCLDTCC' : 32-bit register
|
|
// Register is split into the following bit fields
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//
|
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// [14:0] --> afc_fb_tcc default : 15'b0
|
|
// ------------------------------------------------------
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sirv_gnrl_dfflrd #(15) afcfbtcc_dfflrd (15'b0, afcfbtccwe, wrdata[14:0], afcfbtcc_r, clk, rst_n);
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|
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//update
|
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sirv_gnrl_dfflrd #(15) afcfbtcc_updr_dfflrd (15'b0, updatewe, afcfbtcc_r, afcfbtcc_updr, clk, rst_n);
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|
|
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|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- divrstsel_r Register
|
|
//
|
|
// Write divrstsel_r for 'DIVCFG' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [0] --> divrstsel default : 1'b0
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|
// ------------------------------------------------------
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|
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|
sirv_gnrl_dfflrd #(1) divrstsel_r_dfflrd (1'b0, divcfgwe, wrdata[0], divrstsel_r, clk, rst_n);
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|
|
|
// ------------------------------------------------------
|
|
// -- testclk_r Register
|
|
//
|
|
// Write divclksel_r for 'TCLKCFG' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [1:0] --> testclksel default : 1'b0
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|
// [2] --> testclkoen default : 1'b0
|
|
// ------------------------------------------------------
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|
|
|
sirv_gnrl_dfflrd #(3) testclk_r_dfflrd (3'b0, tclkcfgwe, wrdata[2:0], testclk_r, clk, rst_n);
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|
|
|
// ------------------------------------------------------
|
|
// -- digclksel_r Register
|
|
//
|
|
// Write digclksel_r for 'DIGCLKSEL' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [7:0] --> digclksel default : 1'b0
|
|
// ------------------------------------------------------
|
|
|
|
sirv_gnrl_dfflrd #(8) digclksel_r_dfflrd (8'b0000_0001, dclkselwe, wrdata[7:0], digclksel_r, clk, rst_n);
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|
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- clkrxpd_r Register
|
|
//
|
|
// Write digclksel_r for 'CLKRXPD' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [0:0] --> clkrxpd default : 1'b0
|
|
// ------------------------------------------------------
|
|
|
|
sirv_gnrl_dfflrd #(1) clkrxpd_r_dfflrd (1'b0, clkrxpdwe, wrdata[0], clkrxpd_r, clk, rst_n);
|
|
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- sync_r Register
|
|
//
|
|
// Write divsync_r for 'SYNCFG' : 32-bit register
|
|
// Register is split into the following bit fields
|
|
//
|
|
// [0] --> divsync default : 1'b0
|
|
// [1] --> sync_oe default : 1'b0
|
|
// ------------------------------------------------------
|
|
|
|
sirv_gnrl_dfflrd #(2) sync_dfflrd (2'b0, synccfgwe, wrdata[1:0], sync_r, clk, rst_n);
|
|
|
|
|
|
// ------------------------------------------------------
|
|
// -- Read data mux
|
|
//
|
|
// -- The data from the selected register is
|
|
// -- placed on a zero-padded 32-bit read data bus.
|
|
// ------------------------------------------------------
|
|
always @(*) begin : RDDATA_PROC
|
|
rddata_reg = {32{1'b0}};
|
|
if(refctrlen == H ) rddata_reg[2 :0] = refctrl_r ;
|
|
if(pcnten == H ) rddata_reg[6 :0] = pcnt_r ;
|
|
if(pfdctrlen == H ) rddata_reg[2 :0] = pfdctrl_r ;
|
|
if(spdctrlen == H ) rddata_reg[5 :0] = spdctrl_r ;
|
|
if(ptatctrlen == H ) rddata_reg[6 :0] = ptatctrl_r ;
|
|
if(fllctrlen == H ) rddata_reg[2 :0] = fllctrl_r ;
|
|
if(selctrlen == H ) rddata_reg[2 :0] = selctrl_r ;
|
|
if(vcoctrlen == H ) rddata_reg[11:0] = vcoctrl_r ;
|
|
if(vcofbadjen == H ) rddata_reg[6 :0] = vcofbadj_r ;
|
|
if(afcctrlen == H ) rddata_reg[4 :0] = afcctrl_r ;
|
|
if(afccnten == H ) rddata_reg[10:0] = afccnt_r ;
|
|
if(afcldcnten == H ) rddata_reg[10:0] = afcldcnt_r ;
|
|
if(afcpresen == H ) rddata_reg[3 :0] = afcpres_r ;
|
|
if(afcldtccen == H ) rddata_reg[14:0] = afcldtcc_r ;
|
|
if(afcfbtccen == H ) rddata_reg[14:0] = afcfbtcc_r ;
|
|
if(divcfgen == H ) rddata_reg[0 :0] = divrstsel_r ;
|
|
if(tclkcfgen == H ) rddata_reg[2 :0] = testclk_r ;
|
|
if(dclkselen == H ) rddata_reg[7 :0] = digclksel_r ;
|
|
if(statusen == H ) rddata_reg[0 :0] = pll_lock ;
|
|
if(synccfgen == H ) rddata_reg[1 :0] = sync_r ;
|
|
if(clkrxpden == H ) rddata_reg[1 :0] = clkrxpd_r ;
|
|
|
|
end
|
|
|
|
|
|
//rddata
|
|
sirv_gnrl_dfflr #(32) rddata_dfflr (rden, rddata_reg, rddata, clk, rst_n);
|
|
|
|
// ------------------------------------------------------
|
|
// -- Output signals assignment
|
|
// ------------------------------------------------------
|
|
assign ref_sel = refctrl_updr[0] ; // Clock source selection for a frequency divider;
|
|
// 1'b0:External clock source
|
|
// 1'b1:internal phase-locked loop clock source
|
|
assign ref_en = refctrl_updr[1] ; // Input reference clock enable
|
|
// 1'b0:enable,1'b1:disable
|
|
assign ref_s2d_en = refctrl_updr[2] ; // Referenced clock differential to single-ended conversion enable
|
|
// 1'b0:enable,1'b1:disable
|
|
assign p_cnt = pcnt_updr[6:0] ; // P counter
|
|
assign pfd_delay = pfdctrl_updr[0] ; // PFD Dead Zone
|
|
assign pfd_dff_Set = pfdctrl_updr[1] ; // Setting the PFD register,active high
|
|
assign pfd_dff_4and = pfdctrl_updr[2] ; // PFD output polarity
|
|
assign spd_div = spdctrl_updr[3:0] ; // SPD Frequency Divider
|
|
assign spd_pulse_width = spdctrl_updr[4] ; // Pulse Width of SPD
|
|
assign spd_pulse_sw = spdctrl_updr[5] ; // Pulse sw of SPD
|
|
assign cpc_sel = ptatctrl_updr[6] ; // current source selection
|
|
assign swcp_i = ptatctrl_updr[5:4] ; // PTAT current switch
|
|
assign sw_ptat_r = ptatctrl_updr[3:0] ; // PTAT current adjustment
|
|
assign sw_fll_cpi = fllctrl_updr[1:0] ; // Phase-locked loop charge pump current
|
|
assign sw_fll_delay = fllctrl_updr[2] ; // PLL Dead Zone
|
|
assign pfd_sel = selctrl_updr[0] ; // PFD Loop selection
|
|
assign spd_sel = selctrl_updr[1] ; // SPD Loop selection
|
|
assign fll_sel = selctrl_updr[2] ; // FLL Loop selection
|
|
assign vco_tc = vcoctrl_updr[0] ; // VCO temperature compensation
|
|
assign vco_tcr = vcoctrl_updr[1] ; // VCO temperature compensation resistor
|
|
assign vco_gain_adj = vcoctrl_updr[2] ; // VCO gain adjustment
|
|
assign vco_gain_adj_r = vcoctrl_updr[3] ; // VCO gain adjustment resistor
|
|
assign vco_cur_adj = vcoctrl_updr[6:4] ; // VCO current adjustment
|
|
assign vco_buff_en = vcoctrl_updr[7] ; // VCO buff enable,active high
|
|
assign vco_en = vcoctrl_updr[8] ; // VCO enable,active high
|
|
assign pll_dpwr_adj = vcoctrl_updr[11:9] ; // PLL frequency division output power adjustment
|
|
assign vco_fb_adj = vcofbadj_updr[6:0] ; // VCO frequency band adjustment
|
|
assign afc_en = afcctrl_updr[0] ; // AFC enable
|
|
assign afc_reset = afcctrl_updr[1] ; // AFC reset
|
|
assign afc_shutdown = afcctrl_updr[2] ; // AFC module shutdown signal
|
|
assign flag_out_sel = afcctrl_updr[3] ; // Read and choose the signs
|
|
assign afc_det_speed = afcctrl_updr[4] ; // AFC detection speed
|
|
assign afc_cnt = afccnt_updr[10:0] ; // AFC frequency band adjustment function counter
|
|
// counting time adjustment
|
|
assign afc_ld_cnt = afcldcnt_updr[10:0] ; // Adjust the counting time of the AFC lock detection
|
|
// feature counter
|
|
assign afc_pres = afcpres_updr[3:0] ; // Adjusting the resolution of the AFC comparator
|
|
assign afc_ld_tcc = afcldtcc_updr[14:0] ; // AFC Lock Detection Function Target Cycle Count
|
|
assign afc_fb_tcc = afcfbtcc_updr[14:0] ; // Target number of cycles for AFC frequency band
|
|
// adjustment function
|
|
assign div_rstn_sel = divrstsel_r[0:0] ; //
|
|
assign test_clk_sel = testclk_r[1:0] ; //
|
|
assign test_clk_oen = testclk_r[2] ; //
|
|
assign dig_clk_sel = digclksel_r[7:0] ; //
|
|
|
|
assign div_sync_en = sync_r[0] ; // Frequency Divider Synchronous Clear Enable
|
|
|
|
assign sync_oe = sync_r[1] ; // SYNC signal output enable, hign active
|
|
|
|
assign clkrx_pdn = clkrxpd_r ;
|
|
|
|
endmodule
|
|
|
|
`undef INTPLL_REFCTRL
|
|
`undef INTPLL_PCNT
|
|
`undef INTPLL_PFDCTRL
|
|
`undef INTPLL_SPDCTRL
|
|
`undef INTPLL_PTATCTRL
|
|
`undef INTPLL_FLLCTRL
|
|
`undef INTPLL_SELCTRL
|
|
`undef INTPLL_VCOCTRL
|
|
`undef INTPLL_VCOFBADJ
|
|
`undef INTPLL_AFCCTRL
|
|
`undef INTPLL_AFCCNT
|
|
`undef INTPLL_AFCLDCNT
|
|
`undef INTPLL_AFCPRES
|
|
`undef INTPLL_AFCLDTCC
|
|
`undef INTPLL_AFCFBTCC
|
|
`undef INTPLL_DIVCFG
|
|
`undef INTPLL_TCLKCFG
|
|
`undef INTPLL_DCLKSEL
|
|
`undef INTPLL_STATUS
|
|
`undef INTPLL_SYNCFG
|
|
`undef INTPLL_UPDATE
|