784 lines
49 KiB
Systemverilog
784 lines
49 KiB
Systemverilog
`include "../define/chip_define.v"
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module TB();
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initial begin
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$fsdbDumpfile("TB1.fsdb");
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$fsdbDumpvars(0, TB);
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$fsdbDumpMDA();
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end
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logic clk;
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logic rstn;
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logic clk_rstn;
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logic qbmcu_i_start;
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spi_if spi_if(clk,rstn);
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sysreg_if sys_if(clk,rstn);
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mcureg_if mcu_if(clk,rstn);
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awgreg_if awg_if(clk,rstn);
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pllreg_if pll_if(clk,rstn);
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dacreg_if dac_if(clk,rstn);
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initial begin
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#0;
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rstn = 1'b0;
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clk_rstn = 1'b0;
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clk = 1'b0;
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qbmcu_i_start = 1'b0;
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#10;
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rstn = 1'b1;
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clk_rstn = 1'b1;
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end
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always #0.5 clk = ~clk;
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reg [31:0] cnt;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt <= 32'd0;
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else
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cnt <= cnt + 32'd1;
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initial begin
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wait(cnt[31]==1'b1)
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$finish(0);
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end
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wire miso; // Spi Miso
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wire miso_oen; // Spi Miso output enable
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assign spi_if.miso = (!U_xyz_chip_top.U_iopad.oen) ? miso : 1'bz;
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sram_if#(25,32) mst(clk);
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assign mst.din = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_wrdata;
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assign mst.wren = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_wren ;
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assign mst.addr = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rwaddr;
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assign mst.rden = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rden ;
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assign mst.dout = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rddata;
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//mcu_regfile U2_mcu_regfile (
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// .clk ( clk )
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// ,.rst_n ( rst_n )
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// ,.rwaddr ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].addr[14:0])
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// ,.wrdata ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].din )
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// ,.wren ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].wren )
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// ,.wrmask ( U_xyz_chip_top.U_digital_top.U0_channel_top.preg_o_wrmask )
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// ,.rden ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].rden )
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// ,.rddata ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].slave.dout )
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// ,.fb_st_info ( U_xyz_chip_top.U_digital_top.U0_channel_top.fb_st_in )
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// ,.run_time ( U_xyz_chip_top.U_digital_top.U0_channel_top.run_time )
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// ,.instr_num ( U_xyz_chip_top.U_digital_top.U0_channel_top.instr_num )
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// ,.mcu_param ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_param )
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// ,.mcu_result ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_result )
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// ,.mcu_cwfr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_cwfr )
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// ,.mcu_gapr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_gapr )
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// ,.mcu_ampr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_ampr )
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// ,.mcu_baisr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_baisr )
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// ,.mcu_nco_pha_clr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_nco_pha_clr )
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// ,.mcu_rz_pha ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_rz_pha )
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//);
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`define CH0_FB 2'b10
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////////////////////////////////////////////////////////////////////////////////////////
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//DUT
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////////////////////////////////////////////////////////////////////////////////////////
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wire async_rstn = rstn;
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wire por_rstn = 1'b1;
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logic sync_out ;
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logic [1 :0] ch0_feedback = `CH0_FB;
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wire [4 :0] cfgid = 5'b00000;
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logic irq;
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//------------------------------PLL cfg pin----------------------------------------------------
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logic ref_sel ; // Clock source selection for a frequency divider;
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// 1'b0:External clock source
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// 1'b1:internal phase-locked loop clock source
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logic ref_en ; // Input reference clock enable
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// 1'b0:enable,1'b1:disable
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logic ref_s2d_en ; // Referenced clock differential to single-ended conversion enable
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// 1'b0:enable,1'b1:disable
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logic [6 :0] p_cnt ; // P counter
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logic pfd_delay ; // PFD Dead Zone
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logic pfd_dff_Set ; // Setting the PFD register,active high
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logic pfd_dff_4and ; // PFD output polarity
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logic [3 :0] spd_div ; // SPD Frequency Divider
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logic spd_pulse_width ; // Pulse Width of SPD
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logic spd_pulse_sw ; // Pulse sw of SPD
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logic cpc_sel ; // current source selection
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logic [1 :0] swcp_i ; // PTAT current switch
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logic [3 :0] sw_ptat_r ; // PTAT current adjustment
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logic [1 :0] sw_fll_cpi ; // Phase-locked loop charge pump current
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logic sw_fll_delay ; // PLL Dead Zone
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logic pfd_sel ; // PFD Loop selection
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logic spd_sel ; // SPD Loop selection
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logic fll_sel ; // FLL Loop selection
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logic vco_tc ; // VCO temperature compensation
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logic vco_tcr ; // VCO temperature compensation resistor
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logic vco_gain_adj ; // VCO gain adjustment
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logic vco_gain_adj_r ; // VCO gain adjustment resistor
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logic [2 :0] vco_cur_adj ; // VCO current adjustment
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logic vco_buff_en ; // VCO buff enable,active high
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logic vco_en ; // VCO enable,active high
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logic [2 :0] pll_dpwr_adj ; // PLL frequency division output power adjustment
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logic [6 :0] vco_fb_adj ; // VCO frequency band adjustment
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logic afc_en ; // AFC enable
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logic afc_shutdown ; // AFC module shutdown signal
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logic [0 :0] afc_det_speed ; // AFC detection speed
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logic [0 :0] flag_out_sel ; // Read and choose the signs
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logic afc_reset ; // AFC reset
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logic [10 :0] afc_cnt ; // AFC frequency band adjustment function counter
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// counting time adjustment
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logic [10 :0] afc_ld_cnt ; // Adjust the counting time of the AFC lock detection
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// feature counter
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logic [3 :0] afc_pres ; // Adjusting the resolution of the AFC comparator
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logic [14 :0] afc_ld_tcc ; // AFC Lock Detection Function Target Cycle Count
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logic [14 :0] afc_fb_tcc ; // Target number of cycles for AFC frequency band
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// adjustment function
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logic sync_clr ; // PLL div sync clr,low active
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logic pll_rstn ; // PLL reset,active low
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logic [0 :0] div_rstn_sel ; // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
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logic [1 :0] test_clk_sel ; // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
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logic [0 :0] test_clk_oen ; // test clk output enable, 1'b0:disenable, 1'b1:enable
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logic [7 :0] dig_clk_sel ; // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
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logic clkrx_pdn ;
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logic pll_lock = 1'b1 ; // PLL LOCK
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//DAC cfg
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logic [2 :0] ch0_dac_addr ;
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logic [2 :0] ch0_dac_dw ;
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logic [8 :0] ch0_dac_ref ;
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logic [16 :0] ch0_dac_Prbs_rst0 ;
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logic [16 :0] ch0_dac_Prbs_set0 ;
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logic [16 :0] ch0_dac_Prbs_rst1 ;
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logic [16 :0] ch0_dac_Prbs_set1 ;
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logic ch0_dac_Cal_sig ;
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logic ch0_dac_Cal_rstn ;
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logic ch1_dac_Cal_div_rstn ;
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logic ch0_dac_Cal_end = 1'b1;
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//DSP output
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//`ifdef CHANNEL_XY_ON
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logic [15 :0] ch0_xy_dsp_dout0 ;
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logic [15 :0] ch0_xy_dsp_dout1 ;
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logic [15 :0] ch0_xy_dsp_dout2 ;
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logic [15 :0] ch0_xy_dsp_dout3 ;
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logic [15 :0] ch0_xy_dsp_dout4 ;
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logic [15 :0] ch0_xy_dsp_dout5 ;
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logic [15 :0] ch0_xy_dsp_dout6 ;
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logic [15 :0] ch0_xy_dsp_dout7 ;
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logic [15 :0] ch0_xy_dsp_dout8 ;
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logic [15 :0] ch0_xy_dsp_dout9 ;
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logic [15 :0] ch0_xy_dsp_dout10;
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logic [15 :0] ch0_xy_dsp_dout11;
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logic [15 :0] ch0_xy_dsp_dout12;
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logic [15 :0] ch0_xy_dsp_dout13;
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logic [15 :0] ch0_xy_dsp_dout14;
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logic [15 :0] ch0_xy_dsp_dout15;
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//`endif
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//`ifdef CHANNEL_Z_ON
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logic [15 :0] ch0_z_dsp_dout0 ;
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logic [15 :0] ch0_z_dsp_dout1 ;
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logic [15 :0] ch0_z_dsp_dout2 ;
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logic [15 :0] ch0_z_dsp_dout3 ;
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//`endif
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`ifdef CHANNEL_XY_ON
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logic [14:0] ch0_xy_A_DEM_MSB_OUT0;
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logic [14:0] ch0_xy_A_DEM_MSB_OUT1;
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logic [14:0] ch0_xy_A_DEM_MSB_OUT2;
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logic [14:0] ch0_xy_A_DEM_MSB_OUT3;
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logic [14:0] ch0_xy_A_DEM_MSB_OUT4;
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logic [14:0] ch0_xy_A_DEM_MSB_OUT5;
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logic [14:0] ch0_xy_A_DEM_MSB_OUT6;
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logic [14:0] ch0_xy_A_DEM_MSB_OUT7;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT0;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT1;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT2;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT3;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT4;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT5;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT6;
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logic [14:0] ch0_xy_B_DEM_MSB_OUT7;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT0;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT1;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT2;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT3;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT4;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT5;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT6;
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logic [6 :0] ch0_xy_A_DEM_ISB_OUT7;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT0;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT1;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT2;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT3;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT4;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT5;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT6;
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logic [6 :0] ch0_xy_B_DEM_ISB_OUT7;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT0;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT1;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT2;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT3;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT4;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT5;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT6;
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logic [8 :0] ch0_xy_A_DEM_LSB_OUT7;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT0;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT1;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT2;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT3;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT4;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT5;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT6;
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logic [8 :0] ch0_xy_B_DEM_LSB_OUT7;
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`endif
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`ifdef CHANNEL_Z_ON
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logic [14 :0] ch0_z_DEM_MSB_OUT0;
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logic [14 :0] ch0_z_DEM_MSB_OUT1;
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logic [14 :0] ch0_z_DEM_MSB_OUT2;
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logic [14 :0] ch0_z_DEM_MSB_OUT3;
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logic [6 :0] ch0_z_DEM_ISB_OUT0;
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logic [6 :0] ch0_z_DEM_ISB_OUT1;
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logic [6 :0] ch0_z_DEM_ISB_OUT2;
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logic [6 :0] ch0_z_DEM_ISB_OUT3;
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logic [8 :0] ch0_z_DEM_LSB_OUT0;
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logic [8 :0] ch0_z_DEM_LSB_OUT1;
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logic [8 :0] ch0_z_DEM_LSB_OUT2;
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logic [8 :0] ch0_z_DEM_LSB_OUT3;
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`endif
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////////////////////////////////////////////////////////////////////////////////////////////////////
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xyz_chip_top U_xyz_chip_top (
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.clk ( clk )
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,.por_rstn ( por_rstn )
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,.PI_async_rstn ( async_rstn )
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,.PI_sync_in ( qbmcu_i_start )
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,.PO_sync_out ( sync_out )
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,.PI_ch0_feedback ( ch0_feedback )
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`ifdef CHANNEL_IS_FOUR
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,.PI_ch1_feedback ( ch1_feedback )
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,.PI_ch2_feedback ( ch2_feedback )
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,.PI_ch3_feedback ( ch3_feedback )
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`endif
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,.PI_cfgid ( spi_if.cfgid )
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,.PI_sclk ( spi_if.sclk )
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,.PI_csn ( spi_if.csn )
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,.PI_mosi ( spi_if.mosi )
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,.PO_miso ( miso )
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,.PO_irq ( irq )
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,.ref_sel ( ref_sel )
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,.ref_en ( ref_en )
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,.ref_s2d_en ( ref_s2d_en )
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,.p_cnt ( p_cnt )
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,.pfd_delay ( pfd_delay )
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,.pfd_dff_Set ( pfd_dff_Set )
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,.pfd_dff_4and ( pfd_dff_4and )
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,.spd_div ( spd_div )
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,.spd_pulse_width ( spd_pulse_width )
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,.spd_pulse_sw ( spd_pulse_sw )
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,.cpc_sel ( cpc_sel )
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,.swcp_i ( swcp_i )
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,.sw_ptat_r ( sw_ptat_r )
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,.sw_fll_cpi ( sw_fll_cpi )
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,.sw_fll_delay ( sw_fll_delay )
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,.pfd_sel ( pfd_sel )
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,.spd_sel ( spd_sel )
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,.fll_sel ( fll_sel )
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,.vco_tc ( vco_tc )
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,.vco_tcr ( vco_tcr )
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,.vco_gain_adj ( vco_gain_adj )
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,.vco_gain_adj_r ( vco_gain_adj_r )
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,.vco_cur_adj ( vco_cur_adj )
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,.vco_buff_en ( vco_buff_en )
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,.vco_en ( vco_en )
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,.pll_dpwr_adj ( pll_dpwr_adj )
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,.vco_fb_adj ( vco_fb_adj )
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,.afc_en ( afc_en )
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,.afc_shutdown ( afc_shutdown )
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,.afc_det_speed ( afc_det_speed )
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,.flag_out_sel ( flag_out_sel )
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,.afc_reset ( afc_reset )
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,.afc_cnt ( afc_cnt )
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,.afc_ld_cnt ( afc_ld_cnt )
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,.afc_pres ( afc_pres )
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,.afc_ld_tcc ( afc_ld_tcc )
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,.afc_fb_tcc ( afc_fb_tcc )
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,.sync_clr ( sync_clr )
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,.pll_rstn ( pll_rstn )
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,.div_rstn_sel ( div_rstn_sel )
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,.test_clk_sel ( test_clk_sel )
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,.test_clk_oen ( test_clk_oen )
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,.dig_clk_sel ( dig_clk_sel )
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,.clkrx_pdn ( clkrx_pdn )
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,.pll_lock ( pll_lock )
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,.ch0_dac_addr ( ch0_dac_addr )
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,.ch0_dac_dw ( ch0_dac_dw )
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,.ch0_dac_ref ( ch0_dac_ref )
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,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 )
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,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 )
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,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 )
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,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 )
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,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig )
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,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn )
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,.ch0_dac_Cal_div_rstn ( ch0_dac_Cal_div_rstn )
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,.ch0_dac_Cal_end ( ch0_dac_Cal_end )
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`ifdef CHANNEL_IS_FOUR
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,.ch1_dac_addr ( ch1_dac_addr )
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,.ch1_dac_dw ( ch1_dac_dw )
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,.ch1_dac_ref ( ch1_dac_ref )
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,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 )
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,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 )
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,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 )
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,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 )
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,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig )
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,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn )
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,.ch1_dac_Cal_div_rstn ( ch1_dac_Cal_div_rstn )
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,.ch1_dac_Cal_end ( ch1_dac_Cal_end )
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,.ch2_dac_addr ( ch2_dac_addr )
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,.ch2_dac_dw ( ch2_dac_dw )
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,.ch2_dac_ref ( ch2_dac_ref )
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,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 )
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,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 )
|
|
,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 )
|
|
,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 )
|
|
,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig )
|
|
,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn )
|
|
,.ch2_dac_Cal_div_rstn ( ch2_dac_Cal_div_rstn )
|
|
,.ch2_dac_Cal_end ( ch2_dac_Cal_end )
|
|
,.ch3_dac_dw ( ch3_dac_dw )
|
|
,.ch3_dac_ref ( ch3_dac_ref )
|
|
,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 )
|
|
,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 )
|
|
,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 )
|
|
,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 )
|
|
,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig )
|
|
,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn )
|
|
,.ch0_dac_Cal_div_rstn ( ch3_dac_Cal_div_rstn )
|
|
,.ch3_dac_Cal_end ( ch3_dac_Cal_end )
|
|
`endif
|
|
//------------------------------Ch0 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch0_xy_A_DEM_MSB_OUT0 ( ch0_xy_A_DEM_MSB_OUT0 )
|
|
,.ch0_xy_A_DEM_MSB_OUT1 ( ch0_xy_A_DEM_MSB_OUT1 )
|
|
,.ch0_xy_A_DEM_MSB_OUT2 ( ch0_xy_A_DEM_MSB_OUT2 )
|
|
,.ch0_xy_A_DEM_MSB_OUT3 ( ch0_xy_A_DEM_MSB_OUT3 )
|
|
,.ch0_xy_A_DEM_MSB_OUT4 ( ch0_xy_A_DEM_MSB_OUT4 )
|
|
,.ch0_xy_A_DEM_MSB_OUT5 ( ch0_xy_A_DEM_MSB_OUT5 )
|
|
,.ch0_xy_A_DEM_MSB_OUT6 ( ch0_xy_A_DEM_MSB_OUT6 )
|
|
,.ch0_xy_A_DEM_MSB_OUT7 ( ch0_xy_A_DEM_MSB_OUT7 )
|
|
,.ch0_xy_B_DEM_MSB_OUT0 ( ch0_xy_B_DEM_MSB_OUT0 )
|
|
,.ch0_xy_B_DEM_MSB_OUT1 ( ch0_xy_B_DEM_MSB_OUT1 )
|
|
,.ch0_xy_B_DEM_MSB_OUT2 ( ch0_xy_B_DEM_MSB_OUT2 )
|
|
,.ch0_xy_B_DEM_MSB_OUT3 ( ch0_xy_B_DEM_MSB_OUT3 )
|
|
,.ch0_xy_B_DEM_MSB_OUT4 ( ch0_xy_B_DEM_MSB_OUT4 )
|
|
,.ch0_xy_B_DEM_MSB_OUT5 ( ch0_xy_B_DEM_MSB_OUT5 )
|
|
,.ch0_xy_B_DEM_MSB_OUT6 ( ch0_xy_B_DEM_MSB_OUT6 )
|
|
,.ch0_xy_B_DEM_MSB_OUT7 ( ch0_xy_B_DEM_MSB_OUT7 )
|
|
,.ch0_xy_A_DEM_ISB_OUT0 ( ch0_xy_A_DEM_ISB_OUT0 )
|
|
,.ch0_xy_A_DEM_ISB_OUT1 ( ch0_xy_A_DEM_ISB_OUT1 )
|
|
,.ch0_xy_A_DEM_ISB_OUT2 ( ch0_xy_A_DEM_ISB_OUT2 )
|
|
,.ch0_xy_A_DEM_ISB_OUT3 ( ch0_xy_A_DEM_ISB_OUT3 )
|
|
,.ch0_xy_A_DEM_ISB_OUT4 ( ch0_xy_A_DEM_ISB_OUT4 )
|
|
,.ch0_xy_A_DEM_ISB_OUT5 ( ch0_xy_A_DEM_ISB_OUT5 )
|
|
,.ch0_xy_A_DEM_ISB_OUT6 ( ch0_xy_A_DEM_ISB_OUT6 )
|
|
,.ch0_xy_A_DEM_ISB_OUT7 ( ch0_xy_A_DEM_ISB_OUT7 )
|
|
,.ch0_xy_B_DEM_ISB_OUT0 ( ch0_xy_B_DEM_ISB_OUT0 )
|
|
,.ch0_xy_B_DEM_ISB_OUT1 ( ch0_xy_B_DEM_ISB_OUT1 )
|
|
,.ch0_xy_B_DEM_ISB_OUT2 ( ch0_xy_B_DEM_ISB_OUT2 )
|
|
,.ch0_xy_B_DEM_ISB_OUT3 ( ch0_xy_B_DEM_ISB_OUT3 )
|
|
,.ch0_xy_B_DEM_ISB_OUT4 ( ch0_xy_B_DEM_ISB_OUT4 )
|
|
,.ch0_xy_B_DEM_ISB_OUT5 ( ch0_xy_B_DEM_ISB_OUT5 )
|
|
,.ch0_xy_B_DEM_ISB_OUT6 ( ch0_xy_B_DEM_ISB_OUT6 )
|
|
,.ch0_xy_B_DEM_ISB_OUT7 ( ch0_xy_B_DEM_ISB_OUT7 )
|
|
,.ch0_xy_A_DEM_LSB_OUT0 ( ch0_xy_A_DEM_LSB_OUT0 )
|
|
,.ch0_xy_A_DEM_LSB_OUT1 ( ch0_xy_A_DEM_LSB_OUT1 )
|
|
,.ch0_xy_A_DEM_LSB_OUT2 ( ch0_xy_A_DEM_LSB_OUT2 )
|
|
,.ch0_xy_A_DEM_LSB_OUT3 ( ch0_xy_A_DEM_LSB_OUT3 )
|
|
,.ch0_xy_A_DEM_LSB_OUT4 ( ch0_xy_A_DEM_LSB_OUT4 )
|
|
,.ch0_xy_A_DEM_LSB_OUT5 ( ch0_xy_A_DEM_LSB_OUT5 )
|
|
,.ch0_xy_A_DEM_LSB_OUT6 ( ch0_xy_A_DEM_LSB_OUT6 )
|
|
,.ch0_xy_A_DEM_LSB_OUT7 ( ch0_xy_A_DEM_LSB_OUT7 )
|
|
,.ch0_xy_B_DEM_LSB_OUT0 ( ch0_xy_B_DEM_LSB_OUT0 )
|
|
,.ch0_xy_B_DEM_LSB_OUT1 ( ch0_xy_B_DEM_LSB_OUT1 )
|
|
,.ch0_xy_B_DEM_LSB_OUT2 ( ch0_xy_B_DEM_LSB_OUT2 )
|
|
,.ch0_xy_B_DEM_LSB_OUT3 ( ch0_xy_B_DEM_LSB_OUT3 )
|
|
,.ch0_xy_B_DEM_LSB_OUT4 ( ch0_xy_B_DEM_LSB_OUT4 )
|
|
,.ch0_xy_B_DEM_LSB_OUT5 ( ch0_xy_B_DEM_LSB_OUT5 )
|
|
,.ch0_xy_B_DEM_LSB_OUT6 ( ch0_xy_B_DEM_LSB_OUT6 )
|
|
,.ch0_xy_B_DEM_LSB_OUT7 ( ch0_xy_B_DEM_LSB_OUT7 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch0_z_DEM_MSB_OUT0 ( ch0_z_DEM_MSB_OUT0 )
|
|
,.ch0_z_DEM_MSB_OUT1 ( ch0_z_DEM_MSB_OUT1 )
|
|
,.ch0_z_DEM_MSB_OUT2 ( ch0_z_DEM_MSB_OUT2 )
|
|
,.ch0_z_DEM_MSB_OUT3 ( ch0_z_DEM_MSB_OUT3 )
|
|
,.ch0_z_DEM_ISB_OUT0 ( ch0_z_DEM_ISB_OUT0 )
|
|
,.ch0_z_DEM_ISB_OUT1 ( ch0_z_DEM_ISB_OUT1 )
|
|
,.ch0_z_DEM_ISB_OUT2 ( ch0_z_DEM_ISB_OUT2 )
|
|
,.ch0_z_DEM_ISB_OUT3 ( ch0_z_DEM_ISB_OUT3 )
|
|
,.ch0_z_DEM_LSB_OUT0 ( ch0_z_DEM_LSB_OUT0 )
|
|
,.ch0_z_DEM_LSB_OUT1 ( ch0_z_DEM_LSB_OUT1 )
|
|
,.ch0_z_DEM_LSB_OUT2 ( ch0_z_DEM_LSB_OUT2 )
|
|
,.ch0_z_DEM_LSB_OUT3 ( ch0_z_DEM_LSB_OUT3 )
|
|
`endif
|
|
`ifdef CHANNEL_IS_FOUR
|
|
//------------------------------Ch1 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch1_xy_A_DEM_MSB_OUT0 ( ch1_xy_A_DEM_MSB_OUT0 )
|
|
,.ch1_xy_A_DEM_MSB_OUT1 ( ch1_xy_A_DEM_MSB_OUT1 )
|
|
,.ch1_xy_A_DEM_MSB_OUT2 ( ch1_xy_A_DEM_MSB_OUT2 )
|
|
,.ch1_xy_A_DEM_MSB_OUT3 ( ch1_xy_A_DEM_MSB_OUT3 )
|
|
,.ch1_xy_A_DEM_MSB_OUT4 ( ch1_xy_A_DEM_MSB_OUT4 )
|
|
,.ch1_xy_A_DEM_MSB_OUT5 ( ch1_xy_A_DEM_MSB_OUT5 )
|
|
,.ch1_xy_A_DEM_MSB_OUT6 ( ch1_xy_A_DEM_MSB_OUT6 )
|
|
,.ch1_xy_A_DEM_MSB_OUT7 ( ch1_xy_A_DEM_MSB_OUT7 )
|
|
,.ch1_xy_B_DEM_MSB_OUT0 ( ch1_xy_B_DEM_MSB_OUT0 )
|
|
,.ch1_xy_B_DEM_MSB_OUT1 ( ch1_xy_B_DEM_MSB_OUT1 )
|
|
,.ch1_xy_B_DEM_MSB_OUT2 ( ch1_xy_B_DEM_MSB_OUT2 )
|
|
,.ch1_xy_B_DEM_MSB_OUT3 ( ch1_xy_B_DEM_MSB_OUT3 )
|
|
,.ch1_xy_B_DEM_MSB_OUT4 ( ch1_xy_B_DEM_MSB_OUT4 )
|
|
,.ch1_xy_B_DEM_MSB_OUT5 ( ch1_xy_B_DEM_MSB_OUT5 )
|
|
,.ch1_xy_B_DEM_MSB_OUT6 ( ch1_xy_B_DEM_MSB_OUT6 )
|
|
,.ch1_xy_B_DEM_MSB_OUT7 ( ch1_xy_B_DEM_MSB_OUT7 )
|
|
,.ch1_xy_A_DEM_ISB_OUT0 ( ch1_xy_A_DEM_ISB_OUT0 )
|
|
,.ch1_xy_A_DEM_ISB_OUT1 ( ch1_xy_A_DEM_ISB_OUT1 )
|
|
,.ch1_xy_A_DEM_ISB_OUT2 ( ch1_xy_A_DEM_ISB_OUT2 )
|
|
,.ch1_xy_A_DEM_ISB_OUT3 ( ch1_xy_A_DEM_ISB_OUT3 )
|
|
,.ch1_xy_A_DEM_ISB_OUT4 ( ch1_xy_A_DEM_ISB_OUT4 )
|
|
,.ch1_xy_A_DEM_ISB_OUT5 ( ch1_xy_A_DEM_ISB_OUT5 )
|
|
,.ch1_xy_A_DEM_ISB_OUT6 ( ch1_xy_A_DEM_ISB_OUT6 )
|
|
,.ch1_xy_A_DEM_ISB_OUT7 ( ch1_xy_A_DEM_ISB_OUT7 )
|
|
,.ch1_xy_B_DEM_ISB_OUT0 ( ch1_xy_B_DEM_ISB_OUT0 )
|
|
,.ch1_xy_B_DEM_ISB_OUT1 ( ch1_xy_B_DEM_ISB_OUT1 )
|
|
,.ch1_xy_B_DEM_ISB_OUT2 ( ch1_xy_B_DEM_ISB_OUT2 )
|
|
,.ch1_xy_B_DEM_ISB_OUT3 ( ch1_xy_B_DEM_ISB_OUT3 )
|
|
,.ch1_xy_B_DEM_ISB_OUT4 ( ch1_xy_B_DEM_ISB_OUT4 )
|
|
,.ch1_xy_B_DEM_ISB_OUT5 ( ch1_xy_B_DEM_ISB_OUT5 )
|
|
,.ch1_xy_B_DEM_ISB_OUT6 ( ch1_xy_B_DEM_ISB_OUT6 )
|
|
,.ch1_xy_B_DEM_ISB_OUT7 ( ch1_xy_B_DEM_ISB_OUT7 )
|
|
,.ch1_xy_A_DEM_LSB_OUT0 ( ch1_xy_A_DEM_LSB_OUT0 )
|
|
,.ch1_xy_A_DEM_LSB_OUT1 ( ch1_xy_A_DEM_LSB_OUT1 )
|
|
,.ch1_xy_A_DEM_LSB_OUT2 ( ch1_xy_A_DEM_LSB_OUT2 )
|
|
,.ch1_xy_A_DEM_LSB_OUT3 ( ch1_xy_A_DEM_LSB_OUT3 )
|
|
,.ch1_xy_A_DEM_LSB_OUT4 ( ch1_xy_A_DEM_LSB_OUT4 )
|
|
,.ch1_xy_A_DEM_LSB_OUT5 ( ch1_xy_A_DEM_LSB_OUT5 )
|
|
,.ch1_xy_A_DEM_LSB_OUT6 ( ch1_xy_A_DEM_LSB_OUT6 )
|
|
,.ch1_xy_A_DEM_LSB_OUT7 ( ch1_xy_A_DEM_LSB_OUT7 )
|
|
,.ch1_xy_B_DEM_LSB_OUT0 ( ch1_xy_B_DEM_LSB_OUT0 )
|
|
,.ch1_xy_B_DEM_LSB_OUT1 ( ch1_xy_B_DEM_LSB_OUT1 )
|
|
,.ch1_xy_B_DEM_LSB_OUT2 ( ch1_xy_B_DEM_LSB_OUT2 )
|
|
,.ch1_xy_B_DEM_LSB_OUT3 ( ch1_xy_B_DEM_LSB_OUT3 )
|
|
,.ch1_xy_B_DEM_LSB_OUT4 ( ch1_xy_B_DEM_LSB_OUT4 )
|
|
,.ch1_xy_B_DEM_LSB_OUT5 ( ch1_xy_B_DEM_LSB_OUT5 )
|
|
,.ch1_xy_B_DEM_LSB_OUT6 ( ch1_xy_B_DEM_LSB_OUT6 )
|
|
,.ch1_xy_B_DEM_LSB_OUT7 ( ch1_xy_B_DEM_LSB_OUT7 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch1_z_DEM_MSB_OUT0 ( ch1_z_DEM_MSB_OUT0 )
|
|
,.ch1_z_DEM_MSB_OUT1 ( ch1_z_DEM_MSB_OUT1 )
|
|
,.ch1_z_DEM_MSB_OUT2 ( ch1_z_DEM_MSB_OUT2 )
|
|
,.ch1_z_DEM_MSB_OUT3 ( ch1_z_DEM_MSB_OUT3 )
|
|
,.ch1_z_DEM_ISB_OUT0 ( ch1_z_DEM_ISB_OUT0 )
|
|
,.ch1_z_DEM_ISB_OUT1 ( ch1_z_DEM_ISB_OUT1 )
|
|
,.ch1_z_DEM_ISB_OUT2 ( ch1_z_DEM_ISB_OUT2 )
|
|
,.ch1_z_DEM_ISB_OUT3 ( ch1_z_DEM_ISB_OUT3 )
|
|
,.ch1_z_DEM_LSB_OUT0 ( ch1_z_DEM_LSB_OUT0 )
|
|
,.ch1_z_DEM_LSB_OUT1 ( ch1_z_DEM_LSB_OUT1 )
|
|
,.ch1_z_DEM_LSB_OUT2 ( ch1_z_DEM_LSB_OUT2 )
|
|
,.ch1_z_DEM_LSB_OUT3 ( ch1_z_DEM_LSB_OUT3 )
|
|
`endif
|
|
//------------------------------Ch2 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch2_xy_A_DEM_MSB_OUT0 ( ch2_xy_A_DEM_MSB_OUT0 )
|
|
,.ch2_xy_A_DEM_MSB_OUT1 ( ch2_xy_A_DEM_MSB_OUT1 )
|
|
,.ch2_xy_A_DEM_MSB_OUT2 ( ch2_xy_A_DEM_MSB_OUT2 )
|
|
,.ch2_xy_A_DEM_MSB_OUT3 ( ch2_xy_A_DEM_MSB_OUT3 )
|
|
,.ch2_xy_A_DEM_MSB_OUT4 ( ch2_xy_A_DEM_MSB_OUT4 )
|
|
,.ch2_xy_A_DEM_MSB_OUT5 ( ch2_xy_A_DEM_MSB_OUT5 )
|
|
,.ch2_xy_A_DEM_MSB_OUT6 ( ch2_xy_A_DEM_MSB_OUT6 )
|
|
,.ch2_xy_A_DEM_MSB_OUT7 ( ch2_xy_A_DEM_MSB_OUT7 )
|
|
,.ch2_xy_B_DEM_MSB_OUT0 ( ch2_xy_B_DEM_MSB_OUT0 )
|
|
,.ch2_xy_B_DEM_MSB_OUT1 ( ch2_xy_B_DEM_MSB_OUT1 )
|
|
,.ch2_xy_B_DEM_MSB_OUT2 ( ch2_xy_B_DEM_MSB_OUT2 )
|
|
,.ch2_xy_B_DEM_MSB_OUT3 ( ch2_xy_B_DEM_MSB_OUT3 )
|
|
,.ch2_xy_B_DEM_MSB_OUT4 ( ch2_xy_B_DEM_MSB_OUT4 )
|
|
,.ch2_xy_B_DEM_MSB_OUT5 ( ch2_xy_B_DEM_MSB_OUT5 )
|
|
,.ch2_xy_B_DEM_MSB_OUT6 ( ch2_xy_B_DEM_MSB_OUT6 )
|
|
,.ch2_xy_B_DEM_MSB_OUT7 ( ch2_xy_B_DEM_MSB_OUT7 )
|
|
,.ch2_xy_A_DEM_ISB_OUT0 ( ch2_xy_A_DEM_ISB_OUT0 )
|
|
,.ch2_xy_A_DEM_ISB_OUT1 ( ch2_xy_A_DEM_ISB_OUT1 )
|
|
,.ch2_xy_A_DEM_ISB_OUT2 ( ch2_xy_A_DEM_ISB_OUT2 )
|
|
,.ch2_xy_A_DEM_ISB_OUT3 ( ch2_xy_A_DEM_ISB_OUT3 )
|
|
,.ch2_xy_A_DEM_ISB_OUT4 ( ch2_xy_A_DEM_ISB_OUT4 )
|
|
,.ch2_xy_A_DEM_ISB_OUT5 ( ch2_xy_A_DEM_ISB_OUT5 )
|
|
,.ch2_xy_A_DEM_ISB_OUT6 ( ch2_xy_A_DEM_ISB_OUT6 )
|
|
,.ch2_xy_A_DEM_ISB_OUT7 ( ch2_xy_A_DEM_ISB_OUT7 )
|
|
,.ch2_xy_B_DEM_ISB_OUT0 ( ch2_xy_B_DEM_ISB_OUT0 )
|
|
,.ch2_xy_B_DEM_ISB_OUT1 ( ch2_xy_B_DEM_ISB_OUT1 )
|
|
,.ch2_xy_B_DEM_ISB_OUT2 ( ch2_xy_B_DEM_ISB_OUT2 )
|
|
,.ch2_xy_B_DEM_ISB_OUT3 ( ch2_xy_B_DEM_ISB_OUT3 )
|
|
,.ch2_xy_B_DEM_ISB_OUT4 ( ch2_xy_B_DEM_ISB_OUT4 )
|
|
,.ch2_xy_B_DEM_ISB_OUT5 ( ch2_xy_B_DEM_ISB_OUT5 )
|
|
,.ch2_xy_B_DEM_ISB_OUT6 ( ch2_xy_B_DEM_ISB_OUT6 )
|
|
,.ch2_xy_B_DEM_ISB_OUT7 ( ch2_xy_B_DEM_ISB_OUT7 )
|
|
,.ch2_xy_A_DEM_LSB_OUT0 ( ch2_xy_A_DEM_LSB_OUT0 )
|
|
,.ch2_xy_A_DEM_LSB_OUT1 ( ch2_xy_A_DEM_LSB_OUT1 )
|
|
,.ch2_xy_A_DEM_LSB_OUT2 ( ch2_xy_A_DEM_LSB_OUT2 )
|
|
,.ch2_xy_A_DEM_LSB_OUT3 ( ch2_xy_A_DEM_LSB_OUT3 )
|
|
,.ch2_xy_A_DEM_LSB_OUT4 ( ch2_xy_A_DEM_LSB_OUT4 )
|
|
,.ch2_xy_A_DEM_LSB_OUT5 ( ch2_xy_A_DEM_LSB_OUT5 )
|
|
,.ch2_xy_A_DEM_LSB_OUT6 ( ch2_xy_A_DEM_LSB_OUT6 )
|
|
,.ch2_xy_A_DEM_LSB_OUT7 ( ch2_xy_A_DEM_LSB_OUT7 )
|
|
,.ch2_xy_B_DEM_LSB_OUT0 ( ch2_xy_B_DEM_LSB_OUT0 )
|
|
,.ch2_xy_B_DEM_LSB_OUT1 ( ch2_xy_B_DEM_LSB_OUT1 )
|
|
,.ch2_xy_B_DEM_LSB_OUT2 ( ch2_xy_B_DEM_LSB_OUT2 )
|
|
,.ch2_xy_B_DEM_LSB_OUT3 ( ch2_xy_B_DEM_LSB_OUT3 )
|
|
,.ch2_xy_B_DEM_LSB_OUT4 ( ch2_xy_B_DEM_LSB_OUT4 )
|
|
,.ch2_xy_B_DEM_LSB_OUT5 ( ch2_xy_B_DEM_LSB_OUT5 )
|
|
,.ch2_xy_B_DEM_LSB_OUT6 ( ch2_xy_B_DEM_LSB_OUT6 )
|
|
,.ch2_xy_B_DEM_LSB_OUT7 ( ch2_xy_B_DEM_LSB_OUT7 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch2_z_DEM_MSB_OUT0 ( ch2_z_DEM_MSB_OUT0 )
|
|
,.ch2_z_DEM_MSB_OUT1 ( ch2_z_DEM_MSB_OUT1 )
|
|
,.ch2_z_DEM_MSB_OUT2 ( ch2_z_DEM_MSB_OUT2 )
|
|
,.ch2_z_DEM_MSB_OUT3 ( ch2_z_DEM_MSB_OUT3 )
|
|
,.ch2_z_DEM_ISB_OUT0 ( ch2_z_DEM_ISB_OUT0 )
|
|
,.ch2_z_DEM_ISB_OUT1 ( ch2_z_DEM_ISB_OUT1 )
|
|
,.ch2_z_DEM_ISB_OUT2 ( ch2_z_DEM_ISB_OUT2 )
|
|
,.ch2_z_DEM_ISB_OUT3 ( ch2_z_DEM_ISB_OUT3 )
|
|
,.ch2_z_DEM_LSB_OUT0 ( ch2_z_DEM_LSB_OUT0 )
|
|
,.ch2_z_DEM_LSB_OUT1 ( ch2_z_DEM_LSB_OUT1 )
|
|
,.ch2_z_DEM_LSB_OUT2 ( ch2_z_DEM_LSB_OUT2 )
|
|
,.ch2_z_DEM_LSB_OUT3 ( ch2_z_DEM_LSB_OUT3 )
|
|
`endif
|
|
//------------------------------Ch3 DSP data out----------------------------------------------------
|
|
`ifdef CHANNEL_XY_ON
|
|
,.ch3_xy_A_DEM_MSB_OUT0 ( ch3_xy_A_DEM_MSB_OUT0 )
|
|
,.ch3_xy_A_DEM_MSB_OUT1 ( ch3_xy_A_DEM_MSB_OUT1 )
|
|
,.ch3_xy_A_DEM_MSB_OUT2 ( ch3_xy_A_DEM_MSB_OUT2 )
|
|
,.ch3_xy_A_DEM_MSB_OUT3 ( ch3_xy_A_DEM_MSB_OUT3 )
|
|
,.ch3_xy_A_DEM_MSB_OUT4 ( ch3_xy_A_DEM_MSB_OUT4 )
|
|
,.ch3_xy_A_DEM_MSB_OUT5 ( ch3_xy_A_DEM_MSB_OUT5 )
|
|
,.ch3_xy_A_DEM_MSB_OUT6 ( ch3_xy_A_DEM_MSB_OUT6 )
|
|
,.ch3_xy_A_DEM_MSB_OUT7 ( ch3_xy_A_DEM_MSB_OUT7 )
|
|
,.ch3_xy_B_DEM_MSB_OUT0 ( ch3_xy_B_DEM_MSB_OUT0 )
|
|
,.ch3_xy_B_DEM_MSB_OUT1 ( ch3_xy_B_DEM_MSB_OUT1 )
|
|
,.ch3_xy_B_DEM_MSB_OUT2 ( ch3_xy_B_DEM_MSB_OUT2 )
|
|
,.ch3_xy_B_DEM_MSB_OUT3 ( ch3_xy_B_DEM_MSB_OUT3 )
|
|
,.ch3_xy_B_DEM_MSB_OUT4 ( ch3_xy_B_DEM_MSB_OUT4 )
|
|
,.ch3_xy_B_DEM_MSB_OUT5 ( ch3_xy_B_DEM_MSB_OUT5 )
|
|
,.ch3_xy_B_DEM_MSB_OUT6 ( ch3_xy_B_DEM_MSB_OUT6 )
|
|
,.ch3_xy_B_DEM_MSB_OUT7 ( ch3_xy_B_DEM_MSB_OUT7 )
|
|
,.ch3_xy_A_DEM_ISB_OUT0 ( ch3_xy_A_DEM_ISB_OUT0 )
|
|
,.ch3_xy_A_DEM_ISB_OUT1 ( ch3_xy_A_DEM_ISB_OUT1 )
|
|
,.ch3_xy_A_DEM_ISB_OUT2 ( ch3_xy_A_DEM_ISB_OUT2 )
|
|
,.ch3_xy_A_DEM_ISB_OUT3 ( ch3_xy_A_DEM_ISB_OUT3 )
|
|
,.ch3_xy_A_DEM_ISB_OUT4 ( ch3_xy_A_DEM_ISB_OUT4 )
|
|
,.ch3_xy_A_DEM_ISB_OUT5 ( ch3_xy_A_DEM_ISB_OUT5 )
|
|
,.ch3_xy_A_DEM_ISB_OUT6 ( ch3_xy_A_DEM_ISB_OUT6 )
|
|
,.ch3_xy_A_DEM_ISB_OUT7 ( ch3_xy_A_DEM_ISB_OUT7 )
|
|
,.ch3_xy_B_DEM_ISB_OUT0 ( ch3_xy_B_DEM_ISB_OUT0 )
|
|
,.ch3_xy_B_DEM_ISB_OUT1 ( ch3_xy_B_DEM_ISB_OUT1 )
|
|
,.ch3_xy_B_DEM_ISB_OUT2 ( ch3_xy_B_DEM_ISB_OUT2 )
|
|
,.ch3_xy_B_DEM_ISB_OUT3 ( ch3_xy_B_DEM_ISB_OUT3 )
|
|
,.ch3_xy_B_DEM_ISB_OUT4 ( ch3_xy_B_DEM_ISB_OUT4 )
|
|
,.ch3_xy_B_DEM_ISB_OUT5 ( ch3_xy_B_DEM_ISB_OUT5 )
|
|
,.ch3_xy_B_DEM_ISB_OUT6 ( ch3_xy_B_DEM_ISB_OUT6 )
|
|
,.ch3_xy_B_DEM_ISB_OUT7 ( ch3_xy_B_DEM_ISB_OUT7 )
|
|
,.ch3_xy_A_DEM_LSB_OUT0 ( ch3_xy_A_DEM_LSB_OUT0 )
|
|
,.ch3_xy_A_DEM_LSB_OUT1 ( ch3_xy_A_DEM_LSB_OUT1 )
|
|
,.ch3_xy_A_DEM_LSB_OUT2 ( ch3_xy_A_DEM_LSB_OUT2 )
|
|
,.ch3_xy_A_DEM_LSB_OUT3 ( ch3_xy_A_DEM_LSB_OUT3 )
|
|
,.ch3_xy_A_DEM_LSB_OUT4 ( ch3_xy_A_DEM_LSB_OUT4 )
|
|
,.ch3_xy_A_DEM_LSB_OUT5 ( ch3_xy_A_DEM_LSB_OUT5 )
|
|
,.ch3_xy_A_DEM_LSB_OUT6 ( ch3_xy_A_DEM_LSB_OUT6 )
|
|
,.ch3_xy_A_DEM_LSB_OUT7 ( ch3_xy_A_DEM_LSB_OUT7 )
|
|
,.ch3_xy_B_DEM_LSB_OUT0 ( ch3_xy_B_DEM_LSB_OUT0 )
|
|
,.ch3_xy_B_DEM_LSB_OUT1 ( ch3_xy_B_DEM_LSB_OUT1 )
|
|
,.ch3_xy_B_DEM_LSB_OUT2 ( ch3_xy_B_DEM_LSB_OUT2 )
|
|
,.ch3_xy_B_DEM_LSB_OUT3 ( ch3_xy_B_DEM_LSB_OUT3 )
|
|
,.ch3_xy_B_DEM_LSB_OUT4 ( ch3_xy_B_DEM_LSB_OUT4 )
|
|
,.ch3_xy_B_DEM_LSB_OUT5 ( ch3_xy_B_DEM_LSB_OUT5 )
|
|
,.ch3_xy_B_DEM_LSB_OUT6 ( ch3_xy_B_DEM_LSB_OUT6 )
|
|
,.ch3_xy_B_DEM_LSB_OUT7 ( ch3_xy_B_DEM_LSB_OUT7 )
|
|
`endif
|
|
`ifdef CHANNEL_Z_ON
|
|
,.ch3_z_DEM_MSB_OUT0 ( ch3_z_DEM_MSB_OUT0 )
|
|
,.ch3_z_DEM_MSB_OUT1 ( ch3_z_DEM_MSB_OUT1 )
|
|
,.ch3_z_DEM_MSB_OUT2 ( ch3_z_DEM_MSB_OUT2 )
|
|
,.ch3_z_DEM_MSB_OUT3 ( ch3_z_DEM_MSB_OUT3 )
|
|
,.ch3_z_DEM_ISB_OUT0 ( ch3_z_DEM_ISB_OUT0 )
|
|
,.ch3_z_DEM_ISB_OUT1 ( ch3_z_DEM_ISB_OUT1 )
|
|
,.ch3_z_DEM_ISB_OUT2 ( ch3_z_DEM_ISB_OUT2 )
|
|
,.ch3_z_DEM_ISB_OUT3 ( ch3_z_DEM_ISB_OUT3 )
|
|
,.ch3_z_DEM_LSB_OUT0 ( ch3_z_DEM_LSB_OUT0 )
|
|
,.ch3_z_DEM_LSB_OUT1 ( ch3_z_DEM_LSB_OUT1 )
|
|
,.ch3_z_DEM_LSB_OUT2 ( ch3_z_DEM_LSB_OUT2 )
|
|
,.ch3_z_DEM_LSB_OUT3 ( ch3_z_DEM_LSB_OUT3 )
|
|
`endif
|
|
`endif
|
|
);
|
|
|
|
assign pll_if.ref_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_sel ;
|
|
assign pll_if.ref_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_en ;
|
|
assign pll_if.ref_s2d_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_s2d_en ;
|
|
assign pll_if.p_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.p_cnt ;
|
|
assign pll_if.pfd_delay = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_delay ;
|
|
assign pll_if.pfd_dff_Set = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_dff_Set ;
|
|
assign pll_if.pfd_dff_4and = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_dff_4and ;
|
|
assign pll_if.spd_div = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_div ;
|
|
assign pll_if.spd_pulse_width = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_pulse_width;
|
|
assign pll_if.spd_pulse_sw = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_pulse_sw ;
|
|
assign pll_if.cpc_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.cpc_sel ;
|
|
assign pll_if.swcp_i = U_xyz_chip_top.U_digital_top.U_intpll_regfile.swcp_i ;
|
|
assign pll_if.sw_ptat_r = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_ptat_r ;
|
|
assign pll_if.sw_fll_cpi = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_fll_cpi ;
|
|
assign pll_if.sw_fll_delay = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_fll_delay ;
|
|
assign pll_if.pfd_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_sel ;
|
|
assign pll_if.spd_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_sel ;
|
|
assign pll_if.fll_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.fll_sel ;
|
|
assign pll_if.vco_tc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_tc ;
|
|
assign pll_if.vco_tcr = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_tcr ;
|
|
assign pll_if.vco_gain_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_gain_adj ;
|
|
assign pll_if.vco_gain_adj_r = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_gain_adj_r ;
|
|
assign pll_if.vco_cur_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_cur_adj ;
|
|
assign pll_if.vco_buff_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_buff_en ;
|
|
assign pll_if.vco_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_en ;
|
|
assign pll_if.pll_dpwr_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pll_dpwr_adj ;
|
|
assign pll_if.vco_fb_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_fb_adj ;
|
|
assign pll_if.afc_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_en ;
|
|
assign pll_if.afc_shutdown = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_shutdown ;
|
|
assign pll_if.afc_det_speed = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_det_speed ;
|
|
assign pll_if.flag_out_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.flag_out_sel ;
|
|
assign pll_if.afc_reset = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_reset ;
|
|
assign pll_if.afc_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_cnt ;
|
|
assign pll_if.afc_ld_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_ld_cnt ;
|
|
assign pll_if.afc_pres = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_pres ;
|
|
assign pll_if.afc_ld_tcc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_ld_tcc ;
|
|
assign pll_if.afc_fb_tcc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_fb_tcc ;
|
|
assign pll_if.div_rstn_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.div_rstn_sel ;
|
|
assign pll_if.test_clk_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.test_clk_sel ;
|
|
assign pll_if.test_clk_oen = U_xyz_chip_top.U_digital_top.U_intpll_regfile.test_clk_oen ;
|
|
assign pll_if.dig_clk_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.dig_clk_sel ;
|
|
assign pll_if.div_sync_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.div_sync_en ;
|
|
assign pll_if.sync_oe = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sync_oe ;
|
|
assign pll_if.pll_lock = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pll_lock ;
|
|
|
|
assign dac_if.Prbs = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs ;
|
|
assign dac_if.Set0 = U_xyz_chip_top.U_digital_top.ch0_dac_Set0 ;
|
|
assign dac_if.Set1 = U_xyz_chip_top.U_digital_top.ch0_dac_Set1 ;
|
|
assign dac_if.Set2 = U_xyz_chip_top.U_digital_top.ch0_dac_Set2 ;
|
|
assign dac_if.Set3 = U_xyz_chip_top.U_digital_top.ch0_dac_Set3 ;
|
|
assign dac_if.Set4 = U_xyz_chip_top.U_digital_top.ch0_dac_Set4 ;
|
|
assign dac_if.Set5 = U_xyz_chip_top.U_digital_top.ch0_dac_Set5 ;
|
|
assign dac_if.Set6 = U_xyz_chip_top.U_digital_top.ch0_dac_Set6 ;
|
|
assign dac_if.Set7 = U_xyz_chip_top.U_digital_top.ch0_dac_Set7 ;
|
|
assign dac_if.Set8 = U_xyz_chip_top.U_digital_top.ch0_dac_Set8 ;
|
|
assign dac_if.Set9 = U_xyz_chip_top.U_digital_top.ch0_dac_Set9 ;
|
|
assign dac_if.Set10 = U_xyz_chip_top.U_digital_top.ch0_dac_Set10 ;
|
|
assign dac_if.Set11 = U_xyz_chip_top.U_digital_top.ch0_dac_Set11 ;
|
|
assign dac_if.Set12 = U_xyz_chip_top.U_digital_top.ch0_dac_Set12 ;
|
|
assign dac_if.Set13 = U_xyz_chip_top.U_digital_top.ch0_dac_Set13 ;
|
|
assign dac_if.Set14 = U_xyz_chip_top.U_digital_top.ch0_dac_Set14 ;
|
|
assign dac_if.Set15 = U_xyz_chip_top.U_digital_top.ch0_dac_Set15 ;
|
|
assign dac_if.Dac_addr = U_xyz_chip_top.U_digital_top.ch0_dac_addr ;
|
|
assign dac_if.Dac_dw = U_xyz_chip_top.U_digital_top.ch0_dac_dw ;
|
|
assign dac_if.Dac_ref = U_xyz_chip_top.U_digital_top.ch0_dac_ref ;
|
|
assign dac_if.Prbs_rst0 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_rst0 ;
|
|
assign dac_if.Prbs_set0 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_set0 ;
|
|
assign dac_if.Prbs_rst1 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_rst1 ;
|
|
assign dac_if.Prbs_set1 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_set1 ;
|
|
assign dac_if.Cal_sig = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_sig ;
|
|
assign dac_if.Cal_rstn = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_rstn ;
|
|
assign dac_if.Cal_div_rstn = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_div_rstn;
|
|
assign dac_if.Cal_end = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_end ;
|
|
|
|
assign sys_if.dbg_enable = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_enable ;
|
|
assign sys_if.dbg_data_sel = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_data_sel ;
|
|
assign sys_if.dbg_ch_sel = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_ch_sel ;
|
|
assign sys_if.status[28] = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_upd ;
|
|
assign sys_if.status[ 3] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_proc_cft ;
|
|
assign sys_if.status[ 2] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_ldst_addr_unalgn;
|
|
assign sys_if.status[ 1] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_dec_err ;
|
|
assign sys_if.status[ 0] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_exit_irq ;
|
|
assign sys_if.status[11] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_proc_cft ;
|
|
assign sys_if.status[10] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_ldst_addr_unalgn;
|
|
assign sys_if.status[ 9] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_dec_err ;
|
|
assign sys_if.status[ 8] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_exit_irq ;
|
|
assign sys_if.status[19] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_proc_cft ;
|
|
assign sys_if.status[18] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_ldst_addr_unalgn;
|
|
assign sys_if.status[17] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_dec_err ;
|
|
assign sys_if.status[16] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_exit_irq ;
|
|
assign sys_if.status[27] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_proc_cft ;
|
|
assign sys_if.status[26] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_ldst_addr_unalgn;
|
|
assign sys_if.status[25] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_dec_err ;
|
|
assign sys_if.status[24] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_exit_irq ;
|
|
assign sys_if.soft_rstn[0] = U_xyz_chip_top.U_digital_top.U_system_regfile.sys_soft_rstn ;
|
|
assign sys_if.soft_rstn[1] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_soft_rstn ;
|
|
assign sys_if.soft_rstn[2] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_soft_rstn ;
|
|
assign sys_if.soft_rstn[3] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_soft_rstn ;
|
|
assign sys_if.soft_rstn[4] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_soft_rstn ;
|
|
assign sys_if.irq = U_xyz_chip_top.U_digital_top.U_system_regfile.irq ;
|
|
|
|
|
|
assign mcu_if.wrmask = U_xyz_chip_top.U_digital_top.U0_channel_top.U_mcu_regfile.wrmask ;
|
|
|
|
assign awg_if.fb_st_i = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.fb_st_i ;
|
|
assign awg_if.run_time = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.run_time ;
|
|
assign awg_if.instr_num = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.instr_num ;
|
|
assign awg_if.bais_i_ov = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.bais_i_ov ;
|
|
assign awg_if.bais_q_ov = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.bais_q_ov ;
|
|
assign awg_if.awg_ctrl_fsm_st = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.awg_ctrl_fsm_st ;
|
|
assign awg_if.mcu_param0 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param0 ;
|
|
assign awg_if.mcu_param1 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param1 ;
|
|
assign awg_if.mcu_param2 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param2 ;
|
|
assign awg_if.mcu_param3 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param3 ;
|
|
assign awg_if.mcu_result0 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result0 ;
|
|
assign awg_if.mcu_result1 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result1 ;
|
|
assign awg_if.mcu_result2 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result2 ;
|
|
assign awg_if.mcu_result3 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result3 ;
|
|
assign awg_if.fb_st_o = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.fb_st_o ;
|
|
assign awg_if.mod_sel_sideband = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mod_sel_sideband;
|
|
assign awg_if.qam_nco_clr = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_nco_clr ;
|
|
assign awg_if.qam_nco_sclr_en = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_nco_sclr_en ;
|
|
assign awg_if.qam_fcw = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_fcw ;
|
|
assign awg_if.qam_pha = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_pha ;
|
|
assign awg_if.qam_mod = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_mod ;
|
|
assign awg_if.qam_sel_sideband = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_sel_sideband;
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|
assign awg_if.intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.intp_mode ;
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assign awg_if.role_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.role_sel ;
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assign awg_if.dac_mode_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.dac_mode_sel ;
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assign awg_if.dout_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.dout_sel ;
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wire [15 :0] ch0_mod_data_i = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_i ;
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wire [15 :0] ch0_mod_data_q = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_q ;
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wire ch0_mod_vld = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_vld ;
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wire [511:0] mod_data_c = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_data_c ;
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wire mod_cen = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_cen ;
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case6 test(spi_if,pll_if,dac_if,sys_if,mcu_if,awg_if,mst);
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int seed;
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initial begin
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$value$plusargs("ntb_random_seed=%d", seed);
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end
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endmodule
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