SPI_Test/tb/spi_tb/spi_if.sv

19 lines
218 B
Systemverilog

interface spi_if(input clk,input rstn);
//timeunit 1ns;
//timeprecision 1ps;
logic sclk;
logic csn;
logic mosi;
logic miso;
logic [4:0] cfgid;
endinterface : spi_if