142 lines
2.4 KiB
ArmAsm
142 lines
2.4 KiB
ArmAsm
# See LICENSE for license details.
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#*****************************************************************************
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# icache-alias.S
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#-----------------------------------------------------------------------------
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#
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# Test that instruction memory appears to be physically addressed, i.e.,
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# that disagreements in the low-order VPN and PPN bits don't cause the
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# wrong instruction to be fetched. It also tests that changing a page
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# mapping takes effect without executing FENCE.I.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV64M
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RVTEST_CODE_BEGIN
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li TESTNUM, 2
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# Set up intermediate page tables
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la t0, page_table_3
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srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
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ori t0, t0, PTE_V
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sd t0, page_table_2, t1
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la t0, page_table_2
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srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
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ori t0, t0, PTE_V
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sd t0, page_table_1, t1
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# Set up leaf mappings where va[12] != pa[12]
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la t0, code_page_1
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srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
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ori t0, t0, PTE_V | PTE_X | PTE_A
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sd t0, page_table_3 + 8, t1
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la t0, code_page_2
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srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
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ori t0, t0, PTE_V | PTE_X | PTE_A
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sd t0, page_table_3 + 0, t1
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# Turn on VM
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li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
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la a1, page_table_1
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srl a1, a1, RISCV_PGSHIFT
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or a1, a1, a0
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csrw sptbr, a1
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sfence.vma
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# Enter supervisor mode and make sure correct page is accessed
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la a2, 1f
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csrwi mepc, 0
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li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
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csrs mstatus, a1
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mret
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1:
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li TESTNUM, 2
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addi a0, a0, -321
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bnez a0, fail
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li TESTNUM, 3
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la a2, 1f
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li t0, RISCV_PGSIZE
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csrw mepc, t0
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mret
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1:
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addi a0, a0, -123
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bnez a0, fail
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li TESTNUM, 4
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la a2, 1f
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csrwi mepc, 0
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mret
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.align 2
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1:
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addi a0, a0, -321
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bnez a0, fail
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li TESTNUM, 5
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# Change mapping and try again
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la t0, code_page_1
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srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
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ori t0, t0, PTE_V | PTE_X | PTE_A
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sd t0, page_table_3 + 0, t1
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sfence.vma
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la a2, 1f
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csrwi mepc, 0
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mret
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.align 2
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1:
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addi a0, a0, -123
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bnez a0, fail
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RVTEST_PASS
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TEST_PASSFAIL
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.align 2
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.global mtvec_handler
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mtvec_handler:
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csrr t0, mcause
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add t0, t0, -CAUSE_STORE_PAGE_FAULT
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bnez t0, fail
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jr a2
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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.align 12
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page_table_1: .dword 0
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.align 12
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page_table_2: .dword 0
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.align 12
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page_table_3: .dword 0
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.align 13
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code_page_1:
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li a0, 123
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sw x0, (x0)
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.align 12
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code_page_2:
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li a0, 321
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sw x0, (x0)
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RVTEST_DATA_END
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