216 lines
3.3 KiB
ArmAsm
216 lines
3.3 KiB
ArmAsm
# See LICENSE for license details.
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#*****************************************************************************
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# illegal.S
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#-----------------------------------------------------------------------------
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#
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# Test illegal instruction trap.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV64M
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RVTEST_CODE_BEGIN
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.align 2
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.option norvc
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li TESTNUM, 2
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bad2:
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.word 0
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j fail
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# Skip the rest of the test if S-mode is not present.
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li t0, MSTATUS_MPP
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csrc mstatus, t0
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li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
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csrs mstatus, t1
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csrr t2, mstatus
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and t2, t2, t0
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bne t1, t2, pass
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# Test vectored interrupts if they are supported.
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test_vectored_interrupts:
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csrwi mip, MIP_SSIP
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csrwi mie, MIP_SSIP
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la t0, mtvec_handler + 1
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csrrw s0, mtvec, t0
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csrr t0, mtvec
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andi t0, t0, 1
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beqz t0, msip
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csrsi mstatus, MSTATUS_MIE
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1:
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j 1b
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msip:
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csrw mtvec, s0
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# Delegate supervisor software interrupts so WFI won't stall.
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csrwi mideleg, MIP_SSIP
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# Enter supervisor mode.
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la t0, 1f
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csrw mepc, t0
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li t0, MSTATUS_MPP
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csrc mstatus, t0
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li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
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csrs mstatus, t1
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mret
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1:
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# Make sure WFI doesn't trap when TW=0.
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wfi
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# Check if paging is supported (Set SUM & MXR and read it back)
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and t0, t0, zero
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li t0, (SSTATUS_SUM | SSTATUS_MXR)
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csrc sstatus, t0
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and t1, t1, zero
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li t1, (SSTATUS_SUM | SSTATUS_MXR)
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csrs sstatus, t1
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csrr t2, sstatus
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and t2, t2, t0
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beqz t2, bare_s_1
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csrc sstatus, t0
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# Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
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sfence.vma
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csrr t0, sptbr
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bad5:
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.word 0
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j fail
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bad6:
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# Make sure SFENCE.VMA and sptbr do trap when TVM=1.
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sfence.vma
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j fail
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bad7:
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csrr t0, sptbr
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j fail
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test_tsr:
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# Make sure SRET doesn't trap when TSR=0.
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la t0, bad8
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csrw sepc, t0
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li t0, SSTATUS_SPP
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csrs sstatus, t0
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li t0, SSTATUS_SPIE
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csrc sstatus, t0
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sret
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bad8:
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.word 0
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j fail
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# Make sure SRET does trap when TSR=1.
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la t0, 1f
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csrw sepc, t0
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bad9:
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sret
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1:
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j fail
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j skip_bare_s
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bare_s_1:
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# Make sure SFENCE.VMA trap when TVM=0.
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sfence.vma
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j fail
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bare_s_2:
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# Set TVM=1. TVM should stay 0 and SFENCE.VMA should still trap
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sfence.vma
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j fail
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# And access to satp should not trap
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csrr t0, sptbr
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bare_s_3:
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.word 0
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j fail
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j test_tsr
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skip_bare_s:
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TEST_PASSFAIL
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.align 8
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.global mtvec_handler
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mtvec_handler:
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j synchronous_exception
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j msip
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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j fail
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synchronous_exception:
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li t1, CAUSE_ILLEGAL_INSTRUCTION
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csrr t0, mcause
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bne t0, t1, fail
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csrr t0, mepc
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# Make sure mtval contains either 0 or the instruction word.
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csrr t2, mbadaddr
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beqz t2, 1f
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lhu t1, 0(t0)
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xor t2, t2, t1
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lhu t1, 2(t0)
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slli t1, t1, 16
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xor t2, t2, t1
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bnez t2, fail
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1:
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la t1, bad2
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beq t0, t1, 2f
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la t1, bad5
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beq t0, t1, 5f
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la t1, bad6
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beq t0, t1, 6f
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la t1, bad7
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beq t0, t1, 7f
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la t1, bad8
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beq t0, t1, 8f
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la t1, bad9
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beq t0, t1, 9f
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la t1, bare_s_1
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beq t0, t1, 5f
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la t1, bare_s_2
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beq t0, t1, 7f
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la t1, bare_s_3
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beq t0, t1, 7f
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j fail
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2:
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6:
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7:
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addi t0, t0, 8
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csrw mepc, t0
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mret
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5:
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li t1, MSTATUS_TVM
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csrs mstatus, t1
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j 2b
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8:
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li t1, MSTATUS_TSR
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csrs mstatus, t1
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j 2b
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9:
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j 2b
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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