122 lines
3.6 KiB
Systemverilog
122 lines
3.6 KiB
Systemverilog
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wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
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wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
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wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
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wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
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reg ram_cs_dly1 ;
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reg reg_en_dly1 ;
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always @(posedge ram_clk) begin
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ram_cs_dly1 <= ~ram_cs;
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reg_en_dly1 <= reg_en;
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end
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reg [31:0] temp;
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initial begin
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#1ns;
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//@(posedge ram_cs_dly1 );
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#5ns;
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//while(1)begin
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#1ns;
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REGFILE_CHECK(6'd1 ,32'hffff_f000);
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REGFILE_CHECK(6'd1 ,32'hffff_f7ff);
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REGFILE_CHECK(6'd1 ,32'hffff_fffe);
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REGFILE_CHECK(6'd1 ,32'hffff_ffff);
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REGFILE_CHECK(6'd2 ,32'haaaa_a000);
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REGFILE_CHECK(6'd2 ,32'haaaa_a555);
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REGFILE_CHECK(6'd2 ,32'haaaa_aaaa);
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REGFILE_CHECK(6'd3 ,32'h5555_5000);
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REGFILE_CHECK(6'd3 ,32'h5555_5555);
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REGFILE_CHECK(6'd4 ,32'h1111_1000);
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REGFILE_CHECK(6'd4 ,32'h1111_1111);
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REGFILE_CHECK(6'd5 ,32'h0000_0000);
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REGFILE_CHECK(6'd6 ,32'hffff_f800);
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REGFILE_CHECK(6'd7 ,32'hffff_f855);
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REGFILE_CHECK(6'd8 ,32'hffff_faaa);
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REGFILE_CHECK(6'd9 ,32'hffff_feee);
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REGFILE_CHECK(6'd10,32'hffff_ffff);
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REGFILE_CHECK(6'd11,32'haaaa_ad55);
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REGFILE_CHECK(6'd12,32'haaaa_ad00);
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REGFILE_CHECK(6'd13,32'haaaa_afff);
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REGFILE_CHECK(6'd14,32'haaaa_abbb);
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REGFILE_CHECK(6'd15,32'haaaa_aaaa);
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REGFILE_CHECK(6'd16,32'h5555_52aa);
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REGFILE_CHECK(6'd17,32'h5555_52ff);
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REGFILE_CHECK(6'd18,32'h5555_5000);
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REGFILE_CHECK(6'd19,32'h5555_5444);
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REGFILE_CHECK(6'd20,32'h5555_5555);
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REGFILE_CHECK(6'd21,32'h1111_16ee);
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REGFILE_CHECK(6'd22,32'h1111_16bb);
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REGFILE_CHECK(6'd23,32'h1111_1444);
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REGFILE_CHECK(6'd24,32'h1111_1000);
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REGFILE_CHECK(6'd25,32'h1111_1111);
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REGFILE_CHECK(6'd26,32'h0000_07ff);
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REGFILE_CHECK(6'd27,32'h0000_07aa);
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REGFILE_CHECK(6'd28,32'h0000_0555);
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REGFILE_CHECK(6'd29,32'h0000_0111);
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REGFILE_CHECK(6'd30,32'h0000_0000);
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//@(posedge reg_en_dly1 );
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#10us;
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TEST_PASS;
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end
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task DRAM_DATA_CHECK;
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input [12:0] addr ;
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input [31:0] edata ;
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logic [31:0] ram_data;
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@(posedge ram_cs_dly1 );
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@(posedge ram_clk );
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//$monitor($time, " Simulation time: %t", $time);
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if(ram_cs_dly1) begin
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ram_data = `TB_DRAM.mem[addr];
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//$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
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if(ram_data !== edata) begin
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
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#1us;
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TEST_FAIL;
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end
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
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end
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else begin
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$display("* DRAM CS is High => Error!!!");
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TEST_FAIL;
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end
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endtask
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task REGFILE_CHECK;
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input [4:0] addr ;
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input [31:0] edata ;
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logic [31:0] reg_data;
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@(posedge reg_en );
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@(posedge reg_clk);
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if(reg_en)begin
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reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
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if(reg_data !== edata) begin
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
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#1us;
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TEST_FAIL;
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end
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
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end
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else begin
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$display("* REG WR EN is High => Error!!!");
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TEST_FAIL;
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end
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endtask
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initial begin
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#1000000us;
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$display("\n----------------------------------------\n");
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$display("\t Timeout Error !!!!\n");
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TEST_FAIL;
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end
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