204 lines
6.8 KiB
Systemverilog
204 lines
6.8 KiB
Systemverilog
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wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
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wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
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wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
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wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
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reg ram_cs_dly1 ;
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reg reg_en_dly1 ;
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always @(posedge ram_clk) begin
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ram_cs_dly1 <= ~ram_cs;
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reg_en_dly1 <= reg_en;
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end
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initial begin
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#1ns;
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//@(posedge ram_cs_dly1 );
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#5ns;
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//while(1)begin
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#1ns;
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//@(posedge reg_en_dly1 );
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REGFILE_CHECK(6'd1,32'h0000_1000);
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REGFILE_CHECK(6'd1,32'h0000_1004);
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REGFILE_CHECK(6'd1,32'h0000_1008);
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REGFILE_CHECK(6'd1,32'h0000_100c);
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REGFILE_CHECK(6'd2,32'h0000_1010);
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REGFILE_CHECK(6'd2,32'h0000_1014);
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REGFILE_CHECK(6'd2,32'h0000_1018);
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REGFILE_CHECK(6'd2,32'h0000_101c);
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REGFILE_CHECK(6'd3,32'h0000_1020);
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REGFILE_CHECK(6'd3,32'h0000_1024);
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REGFILE_CHECK(6'd3,32'h0000_1028);
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REGFILE_CHECK(6'd3,32'h0000_102c);
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REGFILE_CHECK(6'd4,32'h0000_1030);
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REGFILE_CHECK(6'd4,32'h0000_1034);
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REGFILE_CHECK(6'd4,32'h0000_1038);
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REGFILE_CHECK(6'd4,32'h0000_103c);
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REGFILE_CHECK(6'd5,32'h0000_1040);
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REGFILE_CHECK(6'd5,32'h0000_1044);
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REGFILE_CHECK(6'd5,32'h0000_1048);
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REGFILE_CHECK(6'd5,32'h0000_104c);
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REGFILE_CHECK(6'd6,32'h0000_1050);
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REGFILE_CHECK(6'd6,32'h0000_1054);
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REGFILE_CHECK(6'd6,32'h0000_1058);
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REGFILE_CHECK(6'd6,32'h0000_105c);
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REGFILE_CHECK(6'd7,32'h0000_1060);
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REGFILE_CHECK(6'd7,32'h0000_1064);
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REGFILE_CHECK(6'd7,32'h0000_1068);
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REGFILE_CHECK(6'd7,32'h0000_106c);
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REGFILE_CHECK(6'd8,32'h0000_1070);
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REGFILE_CHECK(6'd8,32'h0000_1074);
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REGFILE_CHECK(6'd8,32'h0000_1078);
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REGFILE_CHECK(6'd8,32'h0000_107c);
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REGFILE_CHECK(6'd9,32'h0000_1080);
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REGFILE_CHECK(6'd9,32'h0000_1084);
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REGFILE_CHECK(6'd9,32'h0000_1088);
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REGFILE_CHECK(6'd9,32'h0000_108c);
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REGFILE_CHECK(6'd10,32'h0000_1090);
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REGFILE_CHECK(6'd10,32'h0000_1094);
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REGFILE_CHECK(6'd10,32'h0000_1098);
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REGFILE_CHECK(6'd10,32'h0000_109c);
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REGFILE_CHECK(6'd11,32'h0000_10a0);
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REGFILE_CHECK(6'd11,32'h0000_10a4);
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REGFILE_CHECK(6'd11,32'h0000_10a8);
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REGFILE_CHECK(6'd11,32'h0000_10ac);
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REGFILE_CHECK(6'd12,32'h0000_10b0);
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REGFILE_CHECK(6'd12,32'h0000_10b4);
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REGFILE_CHECK(6'd12,32'h0000_10b8);
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REGFILE_CHECK(6'd12,32'h0000_10bc);
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REGFILE_CHECK(6'd13,32'h0000_10c0);
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REGFILE_CHECK(6'd13,32'h0000_10c4);
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REGFILE_CHECK(6'd13,32'h0000_10c8);
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REGFILE_CHECK(6'd13,32'h0000_10cc);
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REGFILE_CHECK(6'd14,32'h0000_10d0);
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REGFILE_CHECK(6'd14,32'h0000_10d4);
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REGFILE_CHECK(6'd14,32'h0000_10d8);
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REGFILE_CHECK(6'd14,32'h0000_10dc);
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REGFILE_CHECK(6'd15,32'h0000_10e0);
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REGFILE_CHECK(6'd15,32'h0000_10e4);
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REGFILE_CHECK(6'd15,32'h0000_10e8);
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REGFILE_CHECK(6'd15,32'h0000_10ec);
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REGFILE_CHECK(6'd16,32'h0000_10f0);
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REGFILE_CHECK(6'd16,32'h0000_10f4);
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REGFILE_CHECK(6'd16,32'h0000_10f8);
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REGFILE_CHECK(6'd16,32'h0000_10fc);
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REGFILE_CHECK(6'd17,32'h0000_1100);
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REGFILE_CHECK(6'd17,32'h0000_1104);
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REGFILE_CHECK(6'd17,32'h0000_1108);
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REGFILE_CHECK(6'd17,32'h0000_110c);
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REGFILE_CHECK(6'd18,32'h0000_1110);
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REGFILE_CHECK(6'd18,32'h0000_1114);
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REGFILE_CHECK(6'd18,32'h0000_1118);
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REGFILE_CHECK(6'd18,32'h0000_111c);
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REGFILE_CHECK(6'd19,32'h0000_1120);
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REGFILE_CHECK(6'd19,32'h0000_1124);
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REGFILE_CHECK(6'd19,32'h0000_1128);
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REGFILE_CHECK(6'd19,32'h0000_112c);
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REGFILE_CHECK(6'd20,32'h0000_1130);
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REGFILE_CHECK(6'd20,32'h0000_1134);
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REGFILE_CHECK(6'd20,32'h0000_1138);
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REGFILE_CHECK(6'd20,32'h0000_113c);
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REGFILE_CHECK(6'd21,32'h0000_1140);
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REGFILE_CHECK(6'd21,32'h0000_1144);
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REGFILE_CHECK(6'd21,32'h0000_1148);
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REGFILE_CHECK(6'd21,32'h0000_114c);
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REGFILE_CHECK(6'd22,32'h0000_1150);
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REGFILE_CHECK(6'd22,32'h0000_1154);
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REGFILE_CHECK(6'd22,32'h0000_1158);
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REGFILE_CHECK(6'd22,32'h0000_115c);
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REGFILE_CHECK(6'd23,32'h0000_1160);
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REGFILE_CHECK(6'd23,32'h0000_1164);
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REGFILE_CHECK(6'd23,32'h0000_1168);
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REGFILE_CHECK(6'd23,32'h0000_116c);
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REGFILE_CHECK(6'd24,32'h0000_1170);
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REGFILE_CHECK(6'd24,32'h0000_1174);
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REGFILE_CHECK(6'd24,32'h0000_1178);
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REGFILE_CHECK(6'd24,32'h0000_117c);
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REGFILE_CHECK(6'd25,32'h0000_1180);
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REGFILE_CHECK(6'd25,32'h0000_1184);
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REGFILE_CHECK(6'd25,32'h0000_1188);
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REGFILE_CHECK(6'd25,32'h0000_118c);
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REGFILE_CHECK(6'd26,32'h0000_1190);
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REGFILE_CHECK(6'd26,32'h0000_1194);
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REGFILE_CHECK(6'd26,32'h0000_1198);
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REGFILE_CHECK(6'd26,32'h0000_119c);
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REGFILE_CHECK(6'd27,32'h0000_11a0);
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REGFILE_CHECK(6'd27,32'h0000_11a4);
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REGFILE_CHECK(6'd27,32'h0000_11a8);
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REGFILE_CHECK(6'd27,32'h0000_11ac);
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REGFILE_CHECK(6'd28,32'h0000_11b0);
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REGFILE_CHECK(6'd28,32'h0000_11b4);
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REGFILE_CHECK(6'd28,32'h0000_11b8);
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REGFILE_CHECK(6'd28,32'h0000_11bc);
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REGFILE_CHECK(6'd29,32'h0000_11c0);
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REGFILE_CHECK(6'd29,32'h0000_11c4);
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REGFILE_CHECK(6'd29,32'h0000_11c8);
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REGFILE_CHECK(6'd29,32'h0000_11cc);
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REGFILE_CHECK(6'd30,32'h0000_11d0);
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REGFILE_CHECK(6'd30,32'h0000_11d4);
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REGFILE_CHECK(6'd30,32'h0000_11d8);
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REGFILE_CHECK(6'd30,32'h0000_11dc);
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REGFILE_CHECK(6'd31,32'h0000_11e0);
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REGFILE_CHECK(6'd31,32'h0000_11e4);
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REGFILE_CHECK(6'd31,32'h0000_11e8);
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REGFILE_CHECK(6'd31,32'h0000_11ec);
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#10us;
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TEST_PASS;
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end
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task DRAM_DATA_CHECK;
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input [9:0] addr ;
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input [31:0] edata ;
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logic [31:0] ram_data;
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@(posedge ram_cs_dly1 );
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@(posedge ram_clk );
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//$monitor($time, " Simulation time: %t", $time);
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if(ram_cs_dly1) begin
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ram_data = `TB_DRAM.mem[addr];
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//$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
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if(ram_data !== edata) begin
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
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#1us;
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TEST_FAIL;
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end
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$display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
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end
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else begin
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$display("* DRAM CS is High => Error!!!");
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TEST_FAIL;
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end
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endtask
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task REGFILE_CHECK;
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input [4:0] addr ;
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input [31:0] edata ;
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logic [31:0] reg_data;
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@(posedge reg_en );
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@(posedge reg_clk);
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if(reg_en)begin
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reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
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if(reg_data !== edata) begin
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
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#1us;
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//TEST_FAIL;
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end
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$display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
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end
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else begin
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$display("* REG WR EN is High => Error!!!");
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//TEST_FAIL;
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end
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endtask
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initial begin
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#100us;
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$display("\n----------------------------------------\n");
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$display("\t Timeout Error !!!!\n");
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TEST_FAIL;
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end
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