74 lines
3.8 KiB
Systemverilog
74 lines
3.8 KiB
Systemverilog
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interface pllreg_if(input clk,input rstn);
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//input port
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logic [31 :0] wrdata // write data
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;logic wren // write enable
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;logic [15 :0] rwaddr // read & write address
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;logic rden // read enable
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;logic pll_lock // PLL LOCK
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//output port
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;logic [31 :0] rddata // read data
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;logic ref_sel // Clock source selection for a frequency divider;
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// 1'b0:External clock source
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// 1'b1:internal phase-locked loop clock source
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;logic ref_en // logic reference clock enable
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// 1'b0:enable;1'b1:disable
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;logic ref_s2d_en // Referenced clock differential to single-ended conversion enable
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// 1'b0:enable;1'b1:disable
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;logic [6 :0] p_cnt // P counter
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;logic pfd_delay // PFD Dead Zone
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;logic pfd_dff_Set // Setting the PFD register;active high
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;logic pfd_dff_4and // PFD logic polarity
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;logic [3 :0] spd_div // SPD Frequency Divider
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;logic spd_pulse_width // Pulse Width of SPD
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;logic spd_pulse_sw // Pulse sw of SPD
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;logic cpc_sel // current source selection
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;logic [1 :0] swcp_i // PTAT current switch
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;logic [3 :0] sw_ptat_r // PTAT current adjustment
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;logic [1 :0] sw_fll_cpi // Phase-locked loop charge pump current
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;logic sw_fll_delay // PLL Dead Zone
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;logic pfd_sel // PFD Loop selection
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;logic spd_sel // SPD Loop selection
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;logic fll_sel // FLL Loop selection
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;logic vco_tc // VCO temperature compensation
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;logic vco_tcr // VCO temperature compensation resistor
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;logic vco_gain_adj // VCO gain adjustment
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;logic vco_gain_adj_r // VCO gain adjustment resistor
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;logic [2 :0] vco_cur_adj // VCO current adjustment
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;logic vco_buff_en // VCO buff enable;active high
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;logic vco_en // VCO enable;active high
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;logic [2 :0] pll_dpwr_adj // PLL frequency division logic power adjustment
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;logic [6 :0] vco_fb_adj // VCO frequency band adjustment
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;logic afc_en // AFC enable
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;logic afc_shutdown // AFC module shutdown signal
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;logic [0 :0] afc_det_speed // AFC detection speed
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;logic [0 :0] flag_out_sel // Read and choose the signs
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;logic afc_reset // AFC reset
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;logic [10 :0] afc_cnt // AFC frequency band adjustment function counter
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// counting time adjustment
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;logic [10 :0] afc_ld_cnt // Adjust the counting time of the AFC lock detection
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// feature counter
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;logic [3 :0] afc_pres // Adjusting the resolution of the AFC comparator
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;logic [14 :0] afc_ld_tcc // AFC Lock Detection Function Target Cycle Count
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;logic [14 :0] afc_fb_tcc // Target number of cycles for AFC frequency band
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// adjustment function
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;logic [0 :0] div_rstn_sel // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
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;logic [1 :0] test_clk_sel // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
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;logic [0 :0] test_clk_oen // test clk output enable, 1'b0:disenable, 1'b1:enable
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;logic [7 :0] dig_clk_sel // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
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;logic [0 :0] div_sync_en // Frequency Divider Synchronous Clear Enable
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;logic sync_oe;
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endinterface : pllreg_if
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