1132 lines
45 KiB
Systemverilog
1132 lines
45 KiB
Systemverilog
`include "chip_define.v"
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//-----------AWG out NCO data------------------
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//1'b0:normal data; 1'b1: NCO data
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`define AWG_OUT 1'b0
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//-------Configure chip role-------------------
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//2'b00:XY's Chiop at AC Mode
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//2'b11:Z's Chiop at DC Mode
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`define ROLE 2'b00
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//-------Interpolation-------------------------
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//Set the interpolation factor
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//3'b000:x1;3'b001:x2;3'b010:x4;
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//3'b011:x8;3'b100:x16;
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`define INTP_MODE 3'b000
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//-----------QAM mode--------------------------
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//Set the mixer output to the mixed signal
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//2'b00:bypass;2'b01:mix;
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//2'b10:cos;2'b11:sin;
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`define QAM_MODE 2'b01
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//-----------sideband select-------------------
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//Set the mixer to upper sideband modulation
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//1'b0:Upper sideband;1'b1:Lower sideband;
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`define MIX_SIDEBAND 1'b0
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//-----------DAC data format--------------------
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//Set the DAC data format to normal mode
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//2'b00:NRZ mode;2'b01:MIX mode;
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//2'b10:2xNRZ mode;2'b00:reserve;
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`define DAC_FORMAT 2'b00
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//define Instr and Envelope ID and envelope data
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//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveCosine_bin.txt"
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`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveCombine_bin.txt"
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//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveFlattop_bin.txt"
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//`define MCU_INSTR_FILE "../../cfgdata/instrmem/awg_inst.txt"
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//`define MCU_INSTR_FILE "../../cfgdata/instrmem/SingleWaveRectangle_bin.txt"
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`define MCU_DATA_FILE "../../cfgdata/datamem/awg_data.txt"
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`define ENVE_ID_FILE "../../cfgdata/enveindex/wave_index_12.txt"
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`define ENVE_DATA_FILE "../../cfgdata/envemem/wave_bin_12.txt"
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`define READ_FILE "../../cfgdata/envemem/rwave_bin_12.txt"
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`define CHIIPID 5'b0_0000
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`define SYSREG_BASEADDR 25'h000_0000
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`define CH0_ITCM_BASEADDR 25'h010_0000
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`define CH0_DTCM_BASEADDR 25'h020_0000
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`define CH0_CTRLREG_BASEADDR 25'h030_0000
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`define CH0_ENVEID_BASEADDR 25'h040_0000
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`define CH0_ENVEMEM_BASEADDR 25'h050_0000
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`define CH0_DACREG_BASEADDR 25'h060_0000
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`define PLL_BASEADDR 25'h1F0_0000
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class BinaryDataReader;
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// 定义一个位队列来存储从TXT文件中读取的32位二进制数据的每一位
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bit spi_data_queue[$];
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// 定义一个方法，用于读取TXT文件并将32位二进制数据按比特存储到队列中
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function void read_txt_file(input string filename);
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int file_id;
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string line;
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bit [31:0] binary_value;
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int i;
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// 打开文件以进行读取
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file_id = $fopen(filename, "r");
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if (file_id == 0) begin
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$display("Error: Failed to open file %s", filename);
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return;
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end
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// 读取文件的每一行，并将其作为32位二进制数据添加到队列中
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while (!$feof(file_id)) begin
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//if ($fgets(line, file_id)) begin
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$fscanf(file_id,"%b\n",binary_value);
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for (i = 31; i >= 0; i--) begin
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spi_data_queue.push_back(binary_value[i]);
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end
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//end
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end
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// 关闭文件
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$fclose(file_id);
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endfunction
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function void get_data_queue(ref bit data_queue[$]);
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data_queue = spi_data_queue;
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spi_data_queue.delete();
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endfunction
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endclass
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class spi_data_send;
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virtual spi_if spi_intf;
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task send_item(bit data_queue[], virtual spi_if spi_intf);
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//ToDo
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//wait(spi_intf.rstn);
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#15ns;
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spi_intf.csn <= 1'b1;
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spi_intf.sclk <= 1'b1;
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#15ns;
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spi_intf.csn <= 1'b0;
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#15ns;
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foreach(data_queue[i]) begin
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spi_intf.mosi <= data_queue[i];
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spi_intf.sclk <= ~spi_intf.sclk;
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#50ns;
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spi_intf.sclk <= ~spi_intf.sclk;
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#50ns;
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end
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spi_intf.sclk <= 1'b1;
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#15ns;
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spi_intf.csn <= 1'b1;
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#100ns;
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endtask : send_item
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endclass
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class spi_reg;
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virtual spi_if spi_intf;
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bit spi_reg_queue[$];
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bit [63:0] write_item;
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int i;
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task write_reg(bit cmd, bit[24:0] addr, bit[4:0] chipid, bit[31:0] data, virtual spi_if spi_intf);
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write_item = {cmd,addr,chipid,1'b0,data};
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$display("write_item %b", write_item);
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for (i = 63; i >= 0; i--) begin
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spi_reg_queue.push_back(write_item[i]);
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$display("write_item %0d: %b", i, write_item[i]);
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end
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foreach (spi_reg_queue[i]) begin
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$display("reg %0d: %b", i, spi_reg_queue[i]);
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end
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//ToDo
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//wait(spi_intf.rstn);
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#15ns;
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spi_intf.csn <= 1'b1;
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spi_intf.sclk <= 1'b1;
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#15ns;
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spi_intf.csn <= 1'b0;
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#15ns;
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foreach(spi_reg_queue[i]) begin
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spi_intf.mosi <= spi_reg_queue[i];
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spi_intf.sclk <= ~spi_intf.sclk;
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#50ns;
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spi_intf.sclk <= ~spi_intf.sclk;
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#50ns;
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end
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spi_intf.sclk <= ~spi_intf.sclk;
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#50ns;
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spi_intf.sclk <= 1'b1;
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#15ns;
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spi_intf.csn <= 1'b1;
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#100ns;
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spi_reg_queue.delete();
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endtask : write_reg
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endclass
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module TB;
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parameter WRITE = 1'b0 ,
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READ = 1'b1 ;
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virtual spi_if vif;
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// 实例化TextFileReader类
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BinaryDataReader data_reader = new();
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spi_data_send spi_send = new();
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spi_reg reg_wr = new();
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//======================================================================
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initial begin
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$fsdbAutoSwitchDumpfile(500, "./verdplus.fsdb", 1000000);
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$fsdbDumpvars();
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end
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//======================================================================
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//clock & reset & bootsel
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//======================================================================
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logic clk ;
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logic rstn ;
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logic clk_rstn ;
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logic qbmcu_i_start ;
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bit data[$];
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parameter SYS_PERIOD = 2;
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//sys_clk --> 50M, 0 phase
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initial begin
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clk =0;
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forever # (SYS_PERIOD/2) clk = ~clk;
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end
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//hresetn
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initial begin
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clk_rstn = 0;
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rstn = 0;
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#1000;
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clk_rstn = 0;
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#1000;
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clk_rstn = 1;
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#1000;
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rstn = 1;
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// $display("m%");
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end
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spi_if aif(.*);
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initial begin
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aif.sclk = 1'b1;
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aif.mosi = 1'b0;
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aif.csn = 1'b1;
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vif = aif;
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end
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initial begin
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qbmcu_i_start = 1'b0;
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wait (rstn);
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////////////////////////////////////////////////////////////
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//reg cfg
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////////////////////////////////////////////////////////////
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//-----------------debug------------------------------
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//DBGCFGR 16'h34
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// dbg_enable = dbgcfgr[0]; 1'b0 -> disable; 1'b1 -> enable;
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// dbg_data_sel = dbgcfgr[1]; 1'b0-->mod;1'b1-->dsp
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// dbg_ch_sel = dbgcfgr[5:2]; //4'b0001-->ch0;4'b0010-->ch1;
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//4'b0100-->ch2;4'b1000-->ch3;
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//6'b0001_0_1
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reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000007,vif);
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//-----------------TC paraneter start------------------------------
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//a_re:
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//tcparr0:'00000000E96476E1'
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//TCPARHR0 16'h130 -> 32'h00000000
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//TCPARLR0 16'h134 -> 32'hE96476E1
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h130,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h134,`CHIIPID,32'hE96476E1,vif);
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//tcparr1:'FFFFFFFF7AC0925C'
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//TCPARHR1 16'h138 -> 32'hFFFFFFFF
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//TCPARLR1 16'h13C -> 32'h7AC0925C
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h138,`CHIIPID,32'hFFFFFFFF,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h13C,`CHIIPID,32'h7AC0925C,vif);
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//tcparr2:'000000016673A91C'
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//TCPARHR2 16'h140 -> 32'h00000001
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//TCPARLR2 16'h144 -> 32'h6673A91C
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h140,`CHIIPID,32'h00000001,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h144,`CHIIPID,32'h6673A91C,vif);
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//tcparr3:'0000000013C11A0B'
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//TCPARHR3 16'h148 -> 32'h00000000
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//TCPARLR3 16'h14C -> 32'h13C11A0B
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h148,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h14C,`CHIIPID,32'h13C11A0B,vif);
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//tcparr4:'0000000000000000'
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//TCPARHR4 16'h150 -> 32'h00000000
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//TCPARLR4 16'h154 -> 32'h00000000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h150,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h154,`CHIIPID,32'h00000000,vif);
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//tcparr5:'0000000000000000'
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//TCPARHR5 16'h158 -> 32'h00000000
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//TCPARLR5 16'h15C -> 32'h00000000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h158,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h15C,`CHIIPID,32'h00000000,vif);
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//a_im:
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//tcpair0:'0000000000000000'
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//TCPAIHR0 16'h160 -> 32'h00000000
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//TCPAILR0 16'h164 -> 32'h00000000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h160,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h164,`CHIIPID,32'h00000000,vif);
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//tcpair1:'FFFFFFFF6405CFFB'
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//TCPAIHR1 16'h168 -> 32'hFFFFFFFF
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//TCPAILR1 16'h16C -> 32'h6405CFFB
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h168,`CHIIPID,32'hFFFFFFFF,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h16C,`CHIIPID,32'h6405CFFB,vif);
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//tcpair2:'FFFFFFFEFEF5F1FF'
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//TCPAIHR2 16'h170 -> 32'hFFFFFFFE
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//TCPAILR2 16'h174 -> 32'hFEF5F1FF
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h170,`CHIIPID,32'hFFFFFFFE,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h174,`CHIIPID,32'hFEF5F1FF,vif);
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//tcpair3:'0000000000000000'
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//TCPAIHR3 16'h178 -> 32'h00000000
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//TCPAILR3 16'h17C -> 32'h00000000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h178,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h17C,`CHIIPID,32'h00000000,vif);
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//tcpair4:'0000000000000000'
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//TCPAIHR4 16'h180 -> 32'h00000000
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//TCPAILR4 16'h184 -> 32'h00000000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h180,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h184,`CHIIPID,32'h00000000,vif);
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//tcpair5:'0000000000000000'
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//TCPAIHR5 16'h188 -> 32'h00000000
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//TCPAILR5 16'h18C -> 32'h00000000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h188,`CHIIPID,32'h00000000,vif);
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h18C,`CHIIPID,32'h00000000,vif);
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//b_re:
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//tcpbrr0:'FFF00E4D'
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//TCPBRR0 16'h190 -> 32'hFFF00E4D
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h190,`CHIIPID,32'hFFF00E4D,vif);
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//tcpbrr1:'FFF02C39'
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//TCPBRR1 16'h194 -> 32'hFFF02C39
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h194,`CHIIPID,32'hFFF02C39,vif);
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//tcpbrr2:'FFF028F5'
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//TCPBRR2 16'h198 -> 32'hFFF028F5
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h198,`CHIIPID,32'hFFF028F5,vif);
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//tcpbrr3:'FFF0008C'
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//TCPBRR3 16'h19C -> 32'hFFF0008C
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h19C,`CHIIPID,32'hFFF0008C,vif);
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//tcpbrr4:'FFF00000'
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//TCPBRR4 16'h1A0 -> 32'hFFF00000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A0,`CHIIPID,32'hFFF00000,vif);
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//tcpbrr5:'FFF00000'
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//TCPBRR5 16'h1A4 -> 32'hFFF00000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A4,`CHIIPID,32'hFFF00000,vif);
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//b_im:
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//tcpbir0:'000000'
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//TCPBIR0 16'h1A8 -> 32'h000000
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1A8,`CHIIPID,32'h000000,vif);
|
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//tcpbir1:'0028DC'
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//TCPBIR1 16'h1AC -> 32'h0028DC
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1AC,`CHIIPID,32'h0028DC,vif);
|
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//tcpbir2:'001140'
|
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//TCPBIR2 16'h1B0 -> 32'h001140
|
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B0,`CHIIPID,32'h001140,vif);
|
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//tcpbir3:'000000'
|
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//TCPBIR3 16'h1B4 -> 32'h000000
|
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B4,`CHIIPID,32'h000000,vif);
|
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//tcpbir4:'000000'
|
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//TCPBIR4 16'h1B8 -> 32'h000000
|
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1B8,`CHIIPID,32'h000000,vif);
|
||
//tcpbir5:'000000'
|
||
//TCPBIR5 16'h1BC -> 32'h000000
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1BC,`CHIIPID,32'h000000,vif);
|
||
//-----------------TC paraneter end------------------------------
|
||
|
||
|
||
//[0]-> 1'b1:Synchronous clear enable for the clock divider
|
||
//[1]-> 1'b1:Enable synchronous signal output
|
||
reg_wr.write_reg(WRITE,`PLL_BASEADDR+32'h4c,`CHIIPID,32'h3,vif);
|
||
|
||
|
||
//Set the chip role to XY
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,`ROLE,vif);
|
||
|
||
|
||
|
||
//Set the chip role to Z & DC mode
|
||
//reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h128,`CHIIPID,32'h0000_0003,vif);
|
||
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||
|
||
//---------------------------INTP----------------------------------------------
|
||
|
||
//Set the interpolation factor
|
||
//3'b000:x1;3'b001:x2;3'b010:x4;
|
||
//3'b011:x8;3'b100:x16;
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||
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h104,`CHIIPID,`INTP_MODE,vif);
|
||
|
||
//---------------------------INTP----------------------------------------------
|
||
|
||
//Enable synchronous clearing for the mixing NCO
|
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reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h190,`CHIIPID,32'h0000_0001,vif);
|
||
|
||
//Set the output data type of the modulator
|
||
//1'b0 --> mod modem data; 1'b1 --> mod nco data for XY DAC
|
||
//1'b0 --> Z dsp data; 1'b1 --> XY dsp data for Z DAC
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h1c4,`CHIIPID,`AWG_OUT,vif);
|
||
|
||
//Set the carrier frequency of the mixing NCO (2GHz)
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h10c,`CHIIPID,32'h2AAA_AAAA,vif);
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h110,`CHIIPID,32'h2AAA_0000,vif);
|
||
|
||
//Set the mixer to upper sideband modulation
|
||
//1'b0:Upper sideband;1'b1:Lower sideband;
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h118,`CHIIPID,`MIX_SIDEBAND,vif);
|
||
|
||
//Set the mixer output to the mixed signal
|
||
//2'b00:bypass;2'b01:mix;
|
||
//2'b10:cos;2'b11:sin;
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h11c,`CHIIPID,`QAM_MODE,vif);
|
||
|
||
//Set the DAC data format to normal mode
|
||
reg_wr.write_reg(WRITE,`CH0_CTRLREG_BASEADDR+32'h120,`CHIIPID,`DAC_FORMAT,vif);
|
||
//2'b00:NRZ mode;2'b01:MIX mode;
|
||
//2'b10:2xNRZ mode;2'b00:reserve;
|
||
|
||
// 调用read_txt_file方法读取TXT文件
|
||
data_reader.read_txt_file(`MCU_INSTR_FILE);
|
||
|
||
// 获取数据队列并打印其内容
|
||
//bit data[$];
|
||
data_reader.get_data_queue(data);
|
||
|
||
foreach (data[i]) begin
|
||
$display("Line %0d: %b", i, data[i]);
|
||
end
|
||
$display("Send MCU_INSTR_FILE");
|
||
spi_send.send_item(data,vif);
|
||
data.delete();
|
||
#100;
|
||
|
||
// 调用read_txt_file方法读取TXT文件
|
||
data_reader.read_txt_file(`MCU_DATA_FILE);
|
||
|
||
// 获取数据队列并打印其内容
|
||
//bit data[$];
|
||
data_reader.get_data_queue(data);
|
||
|
||
foreach (data[i]) begin
|
||
$display("Line %0d: %b", i, data[i]);
|
||
end
|
||
$display("Send MCU_INSTR_FILE");
|
||
spi_send.send_item(data,vif);
|
||
data.delete();
|
||
#100;
|
||
|
||
|
||
data_reader.read_txt_file(`ENVE_ID_FILE);
|
||
data_reader.get_data_queue(data);
|
||
foreach (data[i]) begin
|
||
$display("Line %0d: %b", i, data[i]);
|
||
end
|
||
$display("Send ENVE_ID_FILE");
|
||
spi_send.send_item(data,vif);
|
||
data.delete();
|
||
#100;
|
||
|
||
data_reader.read_txt_file(`ENVE_DATA_FILE);
|
||
data_reader.get_data_queue(data);
|
||
foreach (data[i]) begin
|
||
$display("Line %0d: %b", i, data[i]);
|
||
end
|
||
$display("Send ENVE_DATA1_FILE");
|
||
spi_send.send_item(data,vif);
|
||
data.delete();
|
||
|
||
#100;
|
||
|
||
|
||
|
||
#100;
|
||
qbmcu_i_start = 1'b1;
|
||
#500;
|
||
qbmcu_i_start = 1'b0;
|
||
|
||
#100000;
|
||
|
||
data_reader.read_txt_file(`READ_FILE);
|
||
data_reader.get_data_queue(data);
|
||
|
||
#1000000;
|
||
reg_wr.write_reg(WRITE,`SYSREG_BASEADDR+32'h34,`CHIIPID,32'h00000000,vif);
|
||
foreach (data[i]) begin
|
||
$display("Line %0d: %b", i, data[i]);
|
||
end
|
||
$display("Send READ_FILE");
|
||
spi_send.send_item(data,vif);
|
||
data.delete();
|
||
end
|
||
|
||
|
||
|
||
///////////////////////////////////////////////////////////////////////////////////////////
|
||
//clk gen
|
||
///////////////////////////////////////////////////////////////////////////////////////////
|
||
wire clk_div16_0;
|
||
wire clk_div16_1;
|
||
wire clk_div16_2;
|
||
wire clk_div16_3;
|
||
wire clk_div16_4;
|
||
wire clk_div16_5;
|
||
wire clk_div16_6;
|
||
wire clk_div16_7;
|
||
wire clk_div16_8;
|
||
wire clk_div16_9;
|
||
wire clk_div16_a;
|
||
wire clk_div16_b;
|
||
wire clk_div16_c;
|
||
wire clk_div16_d;
|
||
wire clk_div16_e;
|
||
wire clk_div16_f;
|
||
|
||
|
||
clk_gen inst_clk_gen(
|
||
.rstn (clk_rstn )
|
||
,.clk (clk )
|
||
,.clk_div16_0 (clk_div16_0 )
|
||
,.clk_div16_1 (clk_div16_1 )
|
||
,.clk_div16_2 (clk_div16_2 )
|
||
,.clk_div16_3 (clk_div16_3 )
|
||
,.clk_div16_4 (clk_div16_4 )
|
||
,.clk_div16_5 (clk_div16_5 )
|
||
,.clk_div16_6 (clk_div16_6 )
|
||
,.clk_div16_7 (clk_div16_7 )
|
||
,.clk_div16_8 (clk_div16_8 )
|
||
,.clk_div16_9 (clk_div16_9 )
|
||
,.clk_div16_a (clk_div16_a )
|
||
,.clk_div16_b (clk_div16_b )
|
||
,.clk_div16_c (clk_div16_c )
|
||
,.clk_div16_d (clk_div16_d )
|
||
,.clk_div16_e (clk_div16_e )
|
||
,.clk_div16_f (clk_div16_f )
|
||
,.clk_h (clk_h )
|
||
,.clk_l (clk_l )
|
||
);
|
||
|
||
|
||
|
||
////////////////////////////////////////////////////////////////////////////////////////
|
||
//DUT
|
||
////////////////////////////////////////////////////////////////////////////////////////
|
||
wire async_rstn = rstn;
|
||
wire por_rstn = 1'b1;
|
||
logic sync_out ;
|
||
logic [1 :0] ch0_feedback = 2'b00;
|
||
wire [4 :0] cfgid = 5'b00000;
|
||
logic irq;
|
||
|
||
//------------------------------PLL cfg pin----------------------------------------------------
|
||
logic ref_sel ; // Clock source selection for a frequency divider;
|
||
// 1'b0:External clock source
|
||
// 1'b1:internal phase-locked loop clock source
|
||
logic ref_en ; // Input reference clock enable
|
||
// 1'b0:enable,1'b1:disable
|
||
logic ref_s2d_en ; // Referenced clock differential to single-ended conversion enable
|
||
// 1'b0:enable,1'b1:disable
|
||
logic [6 :0] p_cnt ; // P counter
|
||
logic pfd_delay ; // PFD Dead Zone
|
||
logic pfd_dff_Set ; // Setting the PFD register,active high
|
||
logic pfd_dff_4and ; // PFD output polarity
|
||
logic [3 :0] spd_div ; // SPD Frequency Divider
|
||
logic spd_pulse_width ; // Pulse Width of SPD
|
||
logic spd_pulse_sw ; // Pulse sw of SPD
|
||
logic cpc_sel ; // current source selection
|
||
logic [1 :0] swcp_i ; // PTAT current switch
|
||
logic [3 :0] sw_ptat_r ; // PTAT current adjustment
|
||
logic [1 :0] sw_fll_cpi ; // Phase-locked loop charge pump current
|
||
logic sw_fll_delay ; // PLL Dead Zone
|
||
logic pfd_sel ; // PFD Loop selection
|
||
logic spd_sel ; // SPD Loop selection
|
||
logic fll_sel ; // FLL Loop selection
|
||
logic vco_tc ; // VCO temperature compensation
|
||
logic vco_tcr ; // VCO temperature compensation resistor
|
||
logic vco_gain_adj ; // VCO gain adjustment
|
||
logic vco_gain_adj_r ; // VCO gain adjustment resistor
|
||
logic [2 :0] vco_cur_adj ; // VCO current adjustment
|
||
logic vco_buff_en ; // VCO buff enable,active high
|
||
logic vco_en ; // VCO enable,active high
|
||
logic [2 :0] pll_dpwr_adj ; // PLL frequency division output power adjustment
|
||
logic [6 :0] vco_fb_adj ; // VCO frequency band adjustment
|
||
logic afc_en ; // AFC enable
|
||
logic afc_shutdown ; // AFC module shutdown signal
|
||
logic [0 :0] afc_det_speed ; // AFC detection speed
|
||
logic [0 :0] flag_out_sel ; // Read and choose the signs
|
||
logic afc_reset ; // AFC reset
|
||
logic [10 :0] afc_cnt ; // AFC frequency band adjustment function counter
|
||
// counting time adjustment
|
||
logic [10 :0] afc_ld_cnt ; // Adjust the counting time of the AFC lock detection
|
||
// feature counter
|
||
logic [3 :0] afc_pres ; // Adjusting the resolution of the AFC comparator
|
||
logic [14 :0] afc_ld_tcc ; // AFC Lock Detection Function Target Cycle Count
|
||
logic [14 :0] afc_fb_tcc ; // Target number of cycles for AFC frequency band
|
||
// adjustment function
|
||
logic sync_clr ; // PLL div sync clr,low active
|
||
logic pll_rstn ; // PLL reset,active low
|
||
logic [0 :0] div_rstn_sel ; // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock
|
||
logic [1 :0] test_clk_sel ; // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk
|
||
logic [0 :0] test_clk_oen ; // test clk output enable, 1'b0:disenable, 1'b1:enable
|
||
logic [7 :0] dig_clk_sel ; // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae
|
||
logic clkrx_pdn ;
|
||
logic pll_lock = 1'b1 ; // PLL LOCK
|
||
|
||
//DAC cfg
|
||
logic ch0_dac_Prbs ;
|
||
logic [14 :0] ch0_dac_Set0 ;
|
||
logic [14 :0] ch0_dac_Set1 ;
|
||
logic [14 :0] ch0_dac_Set2 ;
|
||
logic [14 :0] ch0_dac_Set3 ;
|
||
logic [14 :0] ch0_dac_Set4 ;
|
||
logic [14 :0] ch0_dac_Set5 ;
|
||
logic [14 :0] ch0_dac_Set6 ;
|
||
logic [14 :0] ch0_dac_Set7 ;
|
||
logic [14 :0] ch0_dac_Set8 ;
|
||
logic [14 :0] ch0_dac_Set9 ;
|
||
logic [14 :0] ch0_dac_Set10 ;
|
||
logic [14 :0] ch0_dac_Set11 ;
|
||
logic [14 :0] ch0_dac_Set12 ;
|
||
logic [14 :0] ch0_dac_Set13 ;
|
||
logic [14 :0] ch0_dac_Set14 ;
|
||
logic [14 :0] ch0_dac_Set15 ;
|
||
logic [2 :0] ch0_dac_addr ;
|
||
logic [2 :0] ch0_dac_dw ;
|
||
logic [8 :0] ch0_dac_ref ;
|
||
logic [16 :0] ch0_dac_Prbs_rst0 ;
|
||
logic [16 :0] ch0_dac_Prbs_set0 ;
|
||
logic [16 :0] ch0_dac_Prbs_rst1 ;
|
||
logic [16 :0] ch0_dac_Prbs_set1 ;
|
||
logic ch0_dac_Cal_sig ;
|
||
logic ch0_dac_Cal_rstn ;
|
||
logic ch0_dac_Cal_end = 1'b1 ;
|
||
|
||
//DSP output
|
||
//`ifdef CHANNEL_XY_ON
|
||
logic [15 :0] ch0_xy_dsp_dout0 ;
|
||
logic [15 :0] ch0_xy_dsp_dout1 ;
|
||
logic [15 :0] ch0_xy_dsp_dout2 ;
|
||
logic [15 :0] ch0_xy_dsp_dout3 ;
|
||
logic [15 :0] ch0_xy_dsp_dout4 ;
|
||
logic [15 :0] ch0_xy_dsp_dout5 ;
|
||
logic [15 :0] ch0_xy_dsp_dout6 ;
|
||
logic [15 :0] ch0_xy_dsp_dout7 ;
|
||
logic [15 :0] ch0_xy_dsp_dout8 ;
|
||
logic [15 :0] ch0_xy_dsp_dout9 ;
|
||
logic [15 :0] ch0_xy_dsp_dout10 ;
|
||
logic [15 :0] ch0_xy_dsp_dout11 ;
|
||
logic [15 :0] ch0_xy_dsp_dout12 ;
|
||
logic [15 :0] ch0_xy_dsp_dout13 ;
|
||
logic [15 :0] ch0_xy_dsp_dout14 ;
|
||
logic [15 :0] ch0_xy_dsp_dout15 ;
|
||
//`endif
|
||
//`ifdef CHANNEL_Z_ON
|
||
logic [15 :0] ch0_z_dsp_dout0 ;
|
||
logic [15 :0] ch0_z_dsp_dout1 ;
|
||
logic [15 :0] ch0_z_dsp_dout2 ;
|
||
logic [15 :0] ch0_z_dsp_dout3 ;
|
||
//`endif
|
||
|
||
|
||
|
||
digital_top U_digital_top (
|
||
.clk ( clk_div16_0 )
|
||
,.por_rstn ( por_rstn )
|
||
,.async_rstn ( async_rstn )
|
||
,.sync_in ( qbmcu_i_start )
|
||
,.sync_out ( sync_out )
|
||
,.ch0_feedback ( ch0_feedback )
|
||
`ifdef CHANNEL_IS_FOUR
|
||
,.ch1_feedback ( ch1_feedback )
|
||
,.ch2_feedback ( ch2_feedback )
|
||
,.ch3_feedback ( ch3_feedback )
|
||
`endif
|
||
,.cfgid ( cfgid )
|
||
,.sclk ( aif.sclk )
|
||
,.csn ( aif.csn )
|
||
,.mosi ( aif.mosi )
|
||
,.miso ( aif.miso )
|
||
,.oen ( oen )
|
||
,.irq ( irq )
|
||
,.ref_sel ( ref_sel )
|
||
,.ref_en ( ref_en )
|
||
,.ref_s2d_en ( ref_s2d_en )
|
||
,.p_cnt ( p_cnt )
|
||
,.pfd_delay ( pfd_delay )
|
||
,.pfd_dff_Set ( pfd_dff_Set )
|
||
,.pfd_dff_4and ( pfd_dff_4and )
|
||
,.spd_div ( spd_div )
|
||
,.spd_pulse_width ( spd_pulse_width )
|
||
,.spd_pulse_sw ( spd_pulse_sw )
|
||
,.cpc_sel ( cpc_sel )
|
||
,.swcp_i ( swcp_i )
|
||
,.sw_ptat_r ( sw_ptat_r )
|
||
,.sw_fll_cpi ( sw_fll_cpi )
|
||
,.sw_fll_delay ( sw_fll_delay )
|
||
,.pfd_sel ( pfd_sel )
|
||
,.spd_sel ( spd_sel )
|
||
,.fll_sel ( fll_sel )
|
||
,.vco_tc ( vco_tc )
|
||
,.vco_tcr ( vco_tcr )
|
||
,.vco_gain_adj ( vco_gain_adj )
|
||
,.vco_gain_adj_r ( vco_gain_adj_r )
|
||
,.vco_cur_adj ( vco_cur_adj )
|
||
,.vco_buff_en ( vco_buff_en )
|
||
,.vco_en ( vco_en )
|
||
,.pll_dpwr_adj ( pll_dpwr_adj )
|
||
,.vco_fb_adj ( vco_fb_adj )
|
||
,.afc_en ( afc_en )
|
||
,.afc_shutdown ( afc_shutdown )
|
||
,.afc_det_speed ( afc_det_speed )
|
||
,.flag_out_sel ( flag_out_sel )
|
||
,.afc_reset ( afc_reset )
|
||
,.afc_cnt ( afc_cnt )
|
||
,.afc_ld_cnt ( afc_ld_cnt )
|
||
,.afc_pres ( afc_pres )
|
||
,.afc_ld_tcc ( afc_ld_tcc )
|
||
,.afc_fb_tcc ( afc_fb_tcc )
|
||
,.sync_clr ( sync_clr )
|
||
,.pll_rstn ( pll_rstn )
|
||
,.div_rstn_sel ( div_rstn_sel )
|
||
,.test_clk_sel ( test_clk_sel )
|
||
,.test_clk_oen ( test_clk_oen )
|
||
,.dig_clk_sel ( dig_clk_sel )
|
||
,.clkrx_pdn ( clkrx_pdn )
|
||
,.pll_lock ( pll_lock )
|
||
,.ch0_dac_Prbs ( ch0_dac_Prbs )
|
||
,.ch0_dac_Set0 ( ch0_dac_Set0 )
|
||
,.ch0_dac_Set1 ( ch0_dac_Set1 )
|
||
,.ch0_dac_Set2 ( ch0_dac_Set2 )
|
||
,.ch0_dac_Set3 ( ch0_dac_Set3 )
|
||
,.ch0_dac_Set4 ( ch0_dac_Set4 )
|
||
,.ch0_dac_Set5 ( ch0_dac_Set5 )
|
||
,.ch0_dac_Set6 ( ch0_dac_Set6 )
|
||
,.ch0_dac_Set7 ( ch0_dac_Set7 )
|
||
,.ch0_dac_Set8 ( ch0_dac_Set8 )
|
||
,.ch0_dac_Set9 ( ch0_dac_Set9 )
|
||
,.ch0_dac_Set10 ( ch0_dac_Set10 )
|
||
,.ch0_dac_Set11 ( ch0_dac_Set11 )
|
||
,.ch0_dac_Set12 ( ch0_dac_Set12 )
|
||
,.ch0_dac_Set13 ( ch0_dac_Set13 )
|
||
,.ch0_dac_Set14 ( ch0_dac_Set14 )
|
||
,.ch0_dac_Set15 ( ch0_dac_Set15 )
|
||
,.ch0_dac_addr ( ch0_dac_addr )
|
||
,.ch0_dac_dw ( ch0_dac_dw )
|
||
,.ch0_dac_ref ( ch0_dac_ref )
|
||
,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 )
|
||
,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 )
|
||
,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 )
|
||
,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 )
|
||
,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig )
|
||
,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn )
|
||
,.ch0_dac_Cal_end ( ch0_dac_Cal_end )
|
||
`ifdef CHANNEL_IS_FOUR
|
||
,.ch1_dac_Prbs ( ch1_dac_Prbs )
|
||
,.ch1_dac_Set0 ( ch1_dac_Set0 )
|
||
,.ch1_dac_Set1 ( ch1_dac_Set1 )
|
||
,.ch1_dac_Set2 ( ch1_dac_Set2 )
|
||
,.ch1_dac_Set3 ( ch1_dac_Set3 )
|
||
,.ch1_dac_Set4 ( ch1_dac_Set4 )
|
||
,.ch1_dac_Set5 ( ch1_dac_Set5 )
|
||
,.ch1_dac_Set6 ( ch1_dac_Set6 )
|
||
,.ch1_dac_Set7 ( ch1_dac_Set7 )
|
||
,.ch1_dac_Set8 ( ch1_dac_Set8 )
|
||
,.ch1_dac_Set9 ( ch1_dac_Set9 )
|
||
,.ch1_dac_Set10 ( ch1_dac_Set10 )
|
||
,.ch1_dac_Set11 ( ch1_dac_Set11 )
|
||
,.ch1_dac_Set12 ( ch1_dac_Set12 )
|
||
,.ch1_dac_Set13 ( ch1_dac_Set13 )
|
||
,.ch1_dac_Set14 ( ch1_dac_Set14 )
|
||
,.ch1_dac_Set15 ( ch1_dac_Set15 )
|
||
,.ch1_dac_addr ( ch1_dac_addr )
|
||
,.ch1_dac_dw ( ch1_dac_dw )
|
||
,.ch1_dac_ref ( ch1_dac_ref )
|
||
,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 )
|
||
,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 )
|
||
,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 )
|
||
,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 )
|
||
,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig )
|
||
,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn )
|
||
,.ch1_dac_Reset ( ch1_dac_Reset )
|
||
,.ch1_dac_Digitalclk ( ch1_dac_Digitalclk )
|
||
,.ch1_dac_Cal_end ( ch1_dac_Cal_end )
|
||
,.ch2_dac_Prbs ( ch2_dac_Prbs )
|
||
,.ch2_dac_Set0 ( ch2_dac_Set0 )
|
||
,.ch2_dac_Set1 ( ch2_dac_Set1 )
|
||
,.ch2_dac_Set2 ( ch2_dac_Set2 )
|
||
,.ch2_dac_Set3 ( ch2_dac_Set3 )
|
||
,.ch2_dac_Set4 ( ch2_dac_Set4 )
|
||
,.ch2_dac_Set5 ( ch2_dac_Set5 )
|
||
,.ch2_dac_Set6 ( ch2_dac_Set6 )
|
||
,.ch2_dac_Set7 ( ch2_dac_Set7 )
|
||
,.ch2_dac_Set8 ( ch2_dac_Set8 )
|
||
,.ch2_dac_Set9 ( ch2_dac_Set9 )
|
||
,.ch2_dac_Set10 ( ch2_dac_Set10 )
|
||
,.ch2_dac_Set11 ( ch2_dac_Set11 )
|
||
,.ch2_dac_Set12 ( ch2_dac_Set12 )
|
||
,.ch2_dac_Set13 ( ch2_dac_Set13 )
|
||
,.ch2_dac_Set14 ( ch2_dac_Set14 )
|
||
,.ch2_dac_Set15 ( ch2_dac_Set15 )
|
||
,.ch2_dac_addr ( ch2_dac_addr )
|
||
,.ch2_dac_dw ( ch2_dac_dw )
|
||
,.ch2_dac_ref ( ch2_dac_ref )
|
||
,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 )
|
||
,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 )
|
||
,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 )
|
||
,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 )
|
||
,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig )
|
||
,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn )
|
||
,.ch2_dac_Reset ( ch2_dac_Reset )
|
||
,.ch2_dac_Digitalclk ( ch2_dac_Digitalclk )
|
||
,.ch2_dac_Cal_end ( ch2_dac_Cal_end )
|
||
,.ch3_dac_Prbs ( ch3_dac_Prbs )
|
||
,.ch3_dac_Set0 ( ch3_dac_Set0 )
|
||
,.ch3_dac_Set1 ( ch3_dac_Set1 )
|
||
,.ch3_dac_Set2 ( ch3_dac_Set2 )
|
||
,.ch3_dac_Set3 ( ch3_dac_Set3 )
|
||
,.ch3_dac_Set4 ( ch3_dac_Set4 )
|
||
,.ch3_dac_Set5 ( ch3_dac_Set5 )
|
||
,.ch3_dac_Set6 ( ch3_dac_Set6 )
|
||
,.ch3_dac_Set7 ( ch3_dac_Set7 )
|
||
,.ch3_dac_Set8 ( ch3_dac_Set8 )
|
||
,.ch3_dac_Set9 ( ch3_dac_Set9 )
|
||
,.ch3_dac_Set10 ( ch3_dac_Set10 )
|
||
,.ch3_dac_Set11 ( ch3_dac_Set11 )
|
||
,.ch3_dac_Set12 ( ch3_dac_Set12 )
|
||
,.ch3_dac_Set13 ( ch3_dac_Set13 )
|
||
,.ch3_dac_Set14 ( ch3_dac_Set14 )
|
||
,.ch3_dac_Set15 ( ch3_dac_Set15 )
|
||
,.ch3_dac_addr ( ch3_dac_addr )
|
||
,.ch3_dac_dw ( ch3_dac_dw )
|
||
,.ch3_dac_ref ( ch3_dac_ref )
|
||
,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 )
|
||
,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 )
|
||
,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 )
|
||
,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 )
|
||
,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig )
|
||
,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn )
|
||
,.ch3_dac_Reset ( ch3_dac_Reset )
|
||
,.ch3_dac_Digitalclk ( ch3_dac_Digitalclk )
|
||
,.ch3_dac_Cal_end ( ch3_dac_Cal_end )
|
||
`endif
|
||
`ifdef CHANNEL_XY_ON
|
||
,.ch0_xy_dsp_dout0 ( ch0_xy_dsp_dout0 )
|
||
,.ch0_xy_dsp_dout1 ( ch0_xy_dsp_dout1 )
|
||
,.ch0_xy_dsp_dout2 ( ch0_xy_dsp_dout2 )
|
||
,.ch0_xy_dsp_dout3 ( ch0_xy_dsp_dout3 )
|
||
,.ch0_xy_dsp_dout4 ( ch0_xy_dsp_dout4 )
|
||
,.ch0_xy_dsp_dout5 ( ch0_xy_dsp_dout5 )
|
||
,.ch0_xy_dsp_dout6 ( ch0_xy_dsp_dout6 )
|
||
,.ch0_xy_dsp_dout7 ( ch0_xy_dsp_dout7 )
|
||
,.ch0_xy_dsp_dout8 ( ch0_xy_dsp_dout8 )
|
||
,.ch0_xy_dsp_dout9 ( ch0_xy_dsp_dout9 )
|
||
,.ch0_xy_dsp_dout10 ( ch0_xy_dsp_dout10 )
|
||
,.ch0_xy_dsp_dout11 ( ch0_xy_dsp_dout11 )
|
||
,.ch0_xy_dsp_dout12 ( ch0_xy_dsp_dout12 )
|
||
,.ch0_xy_dsp_dout13 ( ch0_xy_dsp_dout13 )
|
||
,.ch0_xy_dsp_dout14 ( ch0_xy_dsp_dout14 )
|
||
,.ch0_xy_dsp_dout15 ( ch0_xy_dsp_dout15 )
|
||
`endif
|
||
`ifdef CHANNEL_Z_ON
|
||
,.ch0_z_dsp_dout0 ( ch0_z_dsp_dout0 )
|
||
,.ch0_z_dsp_dout1 ( ch0_z_dsp_dout1 )
|
||
,.ch0_z_dsp_dout2 ( ch0_z_dsp_dout2 )
|
||
,.ch0_z_dsp_dout3 ( ch0_z_dsp_dout3 )
|
||
`endif
|
||
`ifdef CHANNEL_IS_FOUR
|
||
`ifdef CHANNEL_XY_ON
|
||
,.ch1_xy_dsp_dout0 ( ch1_xy_dsp_dout0 )
|
||
,.ch1_xy_dsp_dout1 ( ch1_xy_dsp_dout1 )
|
||
,.ch1_xy_dsp_dout2 ( ch1_xy_dsp_dout2 )
|
||
,.ch1_xy_dsp_dout3 ( ch1_xy_dsp_dout3 )
|
||
,.ch1_xy_dsp_dout4 ( ch1_xy_dsp_dout4 )
|
||
,.ch1_xy_dsp_dout5 ( ch1_xy_dsp_dout5 )
|
||
,.ch1_xy_dsp_dout6 ( ch1_xy_dsp_dout6 )
|
||
,.ch1_xy_dsp_dout7 ( ch1_xy_dsp_dout7 )
|
||
,.ch1_xy_dsp_dout8 ( ch1_xy_dsp_dout8 )
|
||
,.ch1_xy_dsp_dout9 ( ch1_xy_dsp_dout9 )
|
||
,.ch1_xy_dsp_dout10 ( ch1_xy_dsp_dout10 )
|
||
,.ch1_xy_dsp_dout11 ( ch1_xy_dsp_dout11 )
|
||
,.ch1_xy_dsp_dout12 ( ch1_xy_dsp_dout12 )
|
||
,.ch1_xy_dsp_dout13 ( ch1_xy_dsp_dout13 )
|
||
,.ch1_xy_dsp_dout14 ( ch1_xy_dsp_dout14 )
|
||
,.ch1_xy_dsp_dout15 ( ch1_xy_dsp_dout15 )
|
||
`endif
|
||
`ifdef CHANNEL_Z_ON
|
||
,.ch1_z_dsp_dout0 ( ch1_z_dsp_dout0 )
|
||
,.ch1_z_dsp_dout1 ( ch1_z_dsp_dout1 )
|
||
,.ch1_z_dsp_dout2 ( ch1_z_dsp_dout2 )
|
||
,.ch1_z_dsp_dout3 ( ch1_z_dsp_dout3 )
|
||
`endif
|
||
`ifdef CHANNEL_XY_ON
|
||
,.ch2_xy_dsp_dout0 ( ch2_xy_dsp_dout0 )
|
||
,.ch2_xy_dsp_dout1 ( ch2_xy_dsp_dout1 )
|
||
,.ch2_xy_dsp_dout2 ( ch2_xy_dsp_dout2 )
|
||
,.ch2_xy_dsp_dout3 ( ch2_xy_dsp_dout3 )
|
||
,.ch2_xy_dsp_dout4 ( ch2_xy_dsp_dout4 )
|
||
,.ch2_xy_dsp_dout5 ( ch2_xy_dsp_dout5 )
|
||
,.ch2_xy_dsp_dout6 ( ch2_xy_dsp_dout6 )
|
||
,.ch2_xy_dsp_dout7 ( ch2_xy_dsp_dout7 )
|
||
,.ch2_xy_dsp_dout8 ( ch2_xy_dsp_dout8 )
|
||
,.ch2_xy_dsp_dout9 ( ch2_xy_dsp_dout9 )
|
||
,.ch2_xy_dsp_dout10 ( ch2_xy_dsp_dout10 )
|
||
,.ch2_xy_dsp_dout11 ( ch2_xy_dsp_dout11 )
|
||
,.ch2_xy_dsp_dout12 ( ch2_xy_dsp_dout12 )
|
||
,.ch2_xy_dsp_dout13 ( ch2_xy_dsp_dout13 )
|
||
,.ch2_xy_dsp_dout14 ( ch2_xy_dsp_dout14 )
|
||
,.ch2_xy_dsp_dout15 ( ch2_xy_dsp_dout15 )
|
||
`endif
|
||
`ifdef CHANNEL_Z_ON
|
||
,.ch2_z_dsp_dout0 ( ch2_z_dsp_dout0 )
|
||
,.ch2_z_dsp_dout1 ( ch2_z_dsp_dout1 )
|
||
,.ch2_z_dsp_dout2 ( ch2_z_dsp_dout2 )
|
||
,.ch2_z_dsp_dout3 ( ch2_z_dsp_dout3 )
|
||
`endif
|
||
`ifdef CHANNEL_XY_ON
|
||
,.ch3_xy_dsp_dout0 ( ch3_xy_dsp_dout0 )
|
||
,.ch3_xy_dsp_dout1 ( ch3_xy_dsp_dout1 )
|
||
,.ch3_xy_dsp_dout2 ( ch3_xy_dsp_dout2 )
|
||
,.ch3_xy_dsp_dout3 ( ch3_xy_dsp_dout3 )
|
||
,.ch3_xy_dsp_dout4 ( ch3_xy_dsp_dout4 )
|
||
,.ch3_xy_dsp_dout5 ( ch3_xy_dsp_dout5 )
|
||
,.ch3_xy_dsp_dout6 ( ch3_xy_dsp_dout6 )
|
||
,.ch3_xy_dsp_dout7 ( ch3_xy_dsp_dout7 )
|
||
,.ch3_xy_dsp_dout8 ( ch3_xy_dsp_dout8 )
|
||
,.ch3_xy_dsp_dout9 ( ch3_xy_dsp_dout9 )
|
||
,.ch3_xy_dsp_dout10 ( ch3_xy_dsp_dout10 )
|
||
,.ch3_xy_dsp_dout11 ( ch3_xy_dsp_dout11 )
|
||
,.ch3_xy_dsp_dout12 ( ch3_xy_dsp_dout12 )
|
||
,.ch3_xy_dsp_dout13 ( ch3_xy_dsp_dout13 )
|
||
,.ch3_xy_dsp_dout14 ( ch3_xy_dsp_dout14 )
|
||
,.ch3_xy_dsp_dout15 ( ch3_xy_dsp_dout15 )
|
||
`endif
|
||
`ifdef CHANNEL_Z_ON
|
||
,.ch3_z_dsp_dout0 ( ch3_z_dsp_dout0 )
|
||
,.ch3_z_dsp_dout1 ( ch3_z_dsp_dout1 )
|
||
,.ch3_z_dsp_dout2 ( ch3_z_dsp_dout2 )
|
||
,.ch3_z_dsp_dout3 ( ch3_z_dsp_dout3 )
|
||
`endif
|
||
`endif
|
||
);
|
||
|
||
|
||
logic [31:0] cnt_c;
|
||
|
||
wire add_cnt = 'b1;
|
||
|
||
wire end_cnt = 1'b0;
|
||
|
||
wire [31:0] cnt_n = end_cnt ? 32'h0 :
|
||
add_cnt ? cnt_c + 1'b1 :
|
||
cnt_c ;
|
||
|
||
|
||
sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk_div16_0, async_rstn);
|
||
|
||
initial begin
|
||
wait(cnt_c == 32'd100000);
|
||
$finish(0);
|
||
end
|
||
|
||
|
||
///////////////////////////////////////////////////////////////////////
|
||
//XY DSP output data save
|
||
///////////////////////////////////////////////////////////////////////
|
||
|
||
logic [15:0] cs_wave;
|
||
wire [15:0] i_cs_0 = ch0_xy_dsp_dout0 ;
|
||
wire [15:0] i_cs_1 = ch0_xy_dsp_dout1 ;
|
||
wire [15:0] i_cs_2 = ch0_xy_dsp_dout2 ;
|
||
wire [15:0] i_cs_3 = ch0_xy_dsp_dout3 ;
|
||
wire [15:0] i_cs_4 = ch0_xy_dsp_dout4 ;
|
||
wire [15:0] i_cs_5 = ch0_xy_dsp_dout5 ;
|
||
wire [15:0] i_cs_6 = ch0_xy_dsp_dout6 ;
|
||
wire [15:0] i_cs_7 = ch0_xy_dsp_dout7 ;
|
||
wire [15:0] i_cs_8 = ch0_xy_dsp_dout8 ;
|
||
wire [15:0] i_cs_9 = ch0_xy_dsp_dout9 ;
|
||
wire [15:0] i_cs_a = ch0_xy_dsp_dout10;
|
||
wire [15:0] i_cs_b = ch0_xy_dsp_dout11;
|
||
wire [15:0] i_cs_c = ch0_xy_dsp_dout12;
|
||
wire [15:0] i_cs_d = ch0_xy_dsp_dout13;
|
||
wire [15:0] i_cs_e = ch0_xy_dsp_dout14;
|
||
wire [15:0] i_cs_f = ch0_xy_dsp_dout15;
|
||
|
||
wire [2:0] intp_mode = U_digital_top.U0_channel_top.intp_mode;
|
||
|
||
always@(*)
|
||
fork
|
||
case (intp_mode)
|
||
3'b000 : begin
|
||
@(posedge clk_div16_f)
|
||
cs_wave = i_cs_0;
|
||
end
|
||
3'b001 : begin
|
||
@(posedge clk_div16_f)
|
||
cs_wave = i_cs_0;
|
||
@(posedge clk_div16_7)
|
||
cs_wave = i_cs_1;
|
||
end
|
||
3'b010 : begin
|
||
@(posedge clk_div16_f)
|
||
cs_wave = i_cs_0;
|
||
@(posedge clk_div16_b)
|
||
cs_wave = i_cs_1;
|
||
@(posedge clk_div16_7)
|
||
cs_wave = i_cs_2;
|
||
@(posedge clk_div16_3)
|
||
cs_wave = i_cs_3;
|
||
end
|
||
3'b011 : begin
|
||
@(posedge clk_div16_f)
|
||
cs_wave = i_cs_0;
|
||
@(posedge clk_div16_d)
|
||
cs_wave = i_cs_1;
|
||
@(posedge clk_div16_b)
|
||
cs_wave = i_cs_2;
|
||
@(posedge clk_div16_9)
|
||
cs_wave = i_cs_3;
|
||
@(posedge clk_div16_7)
|
||
cs_wave = i_cs_4;
|
||
@(posedge clk_div16_5)
|
||
cs_wave = i_cs_5;
|
||
@(posedge clk_div16_3)
|
||
cs_wave = i_cs_6;
|
||
@(posedge clk_div16_1)
|
||
cs_wave = i_cs_7;
|
||
end
|
||
3'b100 : begin
|
||
@(posedge clk_div16_f)
|
||
cs_wave = i_cs_0;
|
||
@(posedge clk_div16_e)
|
||
cs_wave = i_cs_1;
|
||
@(posedge clk_div16_d)
|
||
cs_wave = i_cs_2;
|
||
@(posedge clk_div16_c)
|
||
cs_wave = i_cs_3;
|
||
@(posedge clk_div16_b)
|
||
cs_wave = i_cs_4;
|
||
@(posedge clk_div16_a)
|
||
cs_wave = i_cs_5;
|
||
@(posedge clk_div16_9)
|
||
cs_wave = i_cs_6;
|
||
@(posedge clk_div16_8)
|
||
cs_wave = i_cs_7;
|
||
@(posedge clk_div16_7)
|
||
cs_wave = i_cs_8;
|
||
@(posedge clk_div16_6)
|
||
cs_wave = i_cs_9;
|
||
@(posedge clk_div16_5)
|
||
cs_wave = i_cs_a;
|
||
@(posedge clk_div16_4)
|
||
cs_wave = i_cs_b;
|
||
@(posedge clk_div16_3)
|
||
cs_wave = i_cs_c;
|
||
@(posedge clk_div16_2)
|
||
cs_wave = i_cs_d;
|
||
@(posedge clk_div16_1)
|
||
cs_wave = i_cs_e;
|
||
@(posedge clk_div16_0)
|
||
cs_wave = i_cs_f;
|
||
end
|
||
endcase
|
||
join
|
||
|
||
integer XY_fid;
|
||
|
||
always@(posedge clk)
|
||
if(U_digital_top.ch0_xy_dsp_dout_vld)
|
||
$fwrite(XY_fid,"%d\n",cs_wave);
|
||
|
||
///////////////////////////////////////////////////////////////////////
|
||
//Z DSP output data save
|
||
///////////////////////////////////////////////////////////////////////
|
||
|
||
logic [15:0] z_wave;
|
||
wire [15:0] z_cs_0 = ch0_z_dsp_dout0 ;
|
||
wire [15:0] z_cs_1 = ch0_z_dsp_dout1 ;
|
||
wire [15:0] z_cs_2 = ch0_z_dsp_dout2 ;
|
||
wire [15:0] z_cs_3 = ch0_z_dsp_dout3 ;
|
||
|
||
|
||
//wire [2:0] intp_mode = U_digital_top.U0_channel_top.intp_mode;
|
||
|
||
always@(*)
|
||
fork
|
||
case (intp_mode)
|
||
3'b000 : begin
|
||
@(posedge clk_div16_f)
|
||
z_wave = z_cs_0;
|
||
end
|
||
3'b001 : begin
|
||
@(posedge clk_div16_f)
|
||
z_wave = z_cs_0;
|
||
@(posedge clk_div16_7)
|
||
z_wave = z_cs_1;
|
||
end
|
||
3'b010 : begin
|
||
@(posedge clk_div16_f)
|
||
z_wave = z_cs_0;
|
||
@(posedge clk_div16_b)
|
||
z_wave = z_cs_1;
|
||
@(posedge clk_div16_7)
|
||
z_wave = z_cs_2;
|
||
@(posedge clk_div16_3)
|
||
z_wave = z_cs_3;
|
||
end
|
||
endcase
|
||
join
|
||
|
||
integer Z_fid;
|
||
|
||
always@(posedge clk)
|
||
if(cnt_c > 22'd4096)
|
||
$fwrite(Z_fid,"%d\n",z_wave);
|
||
|
||
wire [15 :0] ch0_mod_data_i = U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_i ;
|
||
wire [15 :0] ch0_mod_data_q = U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_q ;
|
||
wire ch0_mod_vld = U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_vld ;
|
||
|
||
integer dbg_mod_fid;
|
||
|
||
initial begin
|
||
#0;
|
||
dbg_mod_fid = $fopen("./dbg_mod_data.dat");
|
||
end
|
||
|
||
always@(posedge clk_div16_0)
|
||
if(ch0_mod_vld)
|
||
$fwrite(dbg_mod_fid,"%h\n",{ch0_mod_data_i,ch0_mod_data_q});
|
||
|
||
wire [511:0] mod_data_c = U_digital_top.U_debug_top.U_debug_sampling.mod_data_c ;
|
||
wire mod_cen = U_digital_top.U_debug_top.U_debug_sampling.mod_cen ;
|
||
|
||
integer dbg_mod_data_c_fid;
|
||
|
||
initial begin
|
||
#0;
|
||
dbg_mod_data_c_fid = $fopen("./dbg_mod_data_c.dat");
|
||
end
|
||
|
||
always@(posedge clk_div16_0)
|
||
if(~mod_cen)
|
||
$fwrite(dbg_mod_data_c_fid,"%h\n",mod_data_c);
|
||
|
||
|
||
endmodule
|
||
|
||
`include "chip_undefine.v"
|
||
|