253 lines
11 KiB
Systemverilog
253 lines
11 KiB
Systemverilog
//For dac_regfile
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class dac_refmodel;
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virtual dacreg_if dif;
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virtual spi_if wif;
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virtual sram_if#(25,32) xif;
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//poor-quality register model
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bit[31:0] rm[29];
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bit[31:0] update_rm[29];
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//members to be sent to scoreboard
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int rst_error[5];
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bit[31:0] dout[$];
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dacreg_trans dacout[$];
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function new();
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endfunction
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extern task do_imitate();
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extern task RWreg_write (bit[24:0] addr,bit[32:0] din );
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extern task ROreg_update (bit[24:0] addr );
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extern task reg_read (bit[24:0] addr );
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extern task rst_check (bit[31:0] rst_time,int i );
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extern task output_trace (bit[24:0] addr );
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endclass : dac_refmodel
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task dac_refmodel::do_imitate();
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int i=0,j=0;
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rm[ 0] = 32'h0; //PRBSCR 16'h0000
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rm[ 1] = 32'h0000413E; //SET0CR 16'h0004
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rm[ 2] = 32'h00003910; //SET1CR 16'h0008
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rm[ 3] = 32'h0000780F; //SET2CR 16'h000C
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rm[ 4] = 32'h00000AD4; //SET3CR 16'h0010
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rm[ 5] = 32'h00000569; //SET4CR 16'h0014
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rm[ 6] = 32'h00006F31; //SET5CR 16'h0018
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rm[ 7] = 32'h00005A38; //SET6CR 16'h001C
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rm[ 8] = 32'h00005660; //SET7CR 16'h0020
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rm[ 9] = 32'h00004F83; //SET8CR 16'h0024
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rm[10] = 32'h00002E95; //SET9CR 16'h0028
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rm[11] = 32'h00005417; //SET10CR 16'h002C
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rm[12] = 32'h000016DE; //SET11CR 16'h0030
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rm[13] = 32'h00000EE9; //SET12CR 16'h0034
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rm[14] = 32'h0000169C; //SET13CR 16'h0038
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rm[15] = 32'h00001135; //SET14CR 16'h003C
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rm[16] = 32'h00005DD1; //SET15CR 16'h0040
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rm[17] = 32'h0; //DACADDR 16'h0044
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rm[18] = 32'h0; //DACDW 16'h0048
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rm[19] = 32'h00000088; //DACREF 16'h004C
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rm[20] = 32'h000001FF; //PRBSRST0 16'h0050
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rm[21] = 32'h0001FE00; //PRBSSET0 16'h0054
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rm[22] = 32'h000000FF; //PRBSRST1 16'h0058
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rm[23] = 32'h0001FF00; //PRBSSET1 16'h005C
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rm[24] = 32'h0; //PRBSREV 16'h0060
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rm[25] = 32'h0; //CALSIG 16'h0064
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rm[26] = 32'h0; //CALEND 16'h0068
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rm[27] = 32'h0; //CALRSTN 16'h006C
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rm[28] = 32'h00000001; //CALDIVRSTN 16'h0070
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fork
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while(1) begin: write_reg_RW
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@(negedge xif.wren);
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RWreg_write(xif.addr,xif.din);
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end: write_reg_RW
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while(1) begin: update_reg_RO
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ROreg_update(xif.addr);
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end: update_reg_RO
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while(1) begin: read_reg
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@(negedge xif.rden);
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repeat(3) @(posedge xif.clk);
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reg_read(xif.addr);
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end: read_reg
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while(1) begin: dbg_port
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@(negedge xif.wren);
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output_trace(xif.addr);
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end: dbg_port
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join
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endtask: do_imitate
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task dac_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din);
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//delay caused by decoder
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@(posedge wif.clk);
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case(addr[24: 2])
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23'h180000: rm[ 0] = {rm[ 0][31: 1],din[0 : 0]}; //PRBSCR 16'h0000
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23'h180001: rm[ 1] = {rm[ 1][31:15],din[14: 0]}; //SET0CR 16'h0004
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23'h180002: rm[ 2] = {rm[ 2][31:15],din[14: 0]}; //SET1CR 16'h0008
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23'h180003: rm[ 3] = {rm[ 3][31:15],din[14: 0]}; //SET2CR 16'h000C
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23'h180004: rm[ 4] = {rm[ 4][31:15],din[14: 0]}; //SET3CR 16'h0010
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23'h180005: rm[ 5] = {rm[ 5][31:15],din[14: 0]}; //SET4CR 16'h0014
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23'h180006: rm[ 6] = {rm[ 6][31:15],din[14: 0]}; //SET5CR 16'h0018
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23'h180007: rm[ 7] = {rm[ 7][31:15],din[14: 0]}; //SET6CR 16'h001C
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23'h180008: rm[ 8] = {rm[ 8][31:15],din[14: 0]}; //SET7CR 16'h0020
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23'h180009: rm[ 9] = {rm[ 9][31:15],din[14: 0]}; //SET8CR 16'h0024
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23'h18000a: rm[10] = {rm[10][31:15],din[14: 0]}; //SET9CR 16'h0028
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23'h18000b: rm[11] = {rm[11][31:15],din[14: 0]}; //SET10CR 16'h002C
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23'h18000c: rm[12] = {rm[12][31:15],din[14: 0]}; //SET11CR 16'h0030
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23'h18000d: rm[13] = {rm[13][31:15],din[14: 0]}; //SET12CR 16'h0034
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23'h18000e: rm[14] = {rm[14][31:15],din[14: 0]}; //SET13CR 16'h0038
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23'h18000f: rm[15] = {rm[15][31:15],din[14: 0]}; //SET14CR 16'h003C
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23'h180010: rm[16] = {rm[16][31:15],din[14: 0]}; //SET15CR 16'h0040
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23'h180011: rm[17] = {rm[17][31: 3],din[ 2: 0]}; //DACADDR 16'h0044
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23'h180012: rm[18] = {rm[18][31: 3],din[ 2: 0]}; //DACDW 16'h0048
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23'h180013: rm[19] = {rm[19][31: 9],din[ 8: 0]}; //DACREF 16'h004C
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23'h180014: rm[20] = {rm[20][31:17],din[16: 0]}; //PRBSRST0 16'h0050
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23'h180015: rm[21] = {rm[21][31:17],din[16: 0]}; //PRBSSET0 16'h0054
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23'h180016: rm[22] = {rm[22][31:17],din[16: 0]}; //PRBSRST1 16'h0058
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23'h180017: rm[23] = {rm[23][31:17],din[16: 0]}; //PRBSSET1 16'h005C
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23'h180018:begin //PRBSREV 16'h0060
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rm[20] = 0; //PRBSRST0 16'h0050
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rm[21] = 0; //PRBSSET0 16'h0054
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rm[22] = 0; //PRBSRST1 16'h0058
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rm[23] = 0; //PRBSSET1 16'h005C
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end
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23'h180019: rm[25] = {rm[25][31: 1],din[ 0: 0]}; //CALSIG 16'h0064
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23'h18001b: rm[27] = {rm[27][31: 1],din[ 0: 0]}; //CALRSTN 16'h006C
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23'h18001c: rm[28] = {rm[28][31: 1],din[ 0: 0]}; //CALDIVRSTN 16'h0070
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endcase
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// $display("addr:%0h",addr);
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// $display("rm:%h",rm[addr[15: 2]]);
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// $display("din:%h",din);
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endtask: RWreg_write
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task dac_refmodel::ROreg_update(bit[24:0] addr);
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@(posedge wif.clk);
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update_rm[26] = dif.Cal_end; //CALEND 16'h0068
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endtask: ROreg_update
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task dac_refmodel::reg_read(bit[24:0] addr);
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@(posedge wif.clk);
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case(addr[24: 2])
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23'h180000: dout.push_back(rm[ 0]); //PRBSCR 16'h0000
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23'h180001: dout.push_back(rm[ 1]); //SET0CR 16'h0004
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23'h180002: dout.push_back(rm[ 2]); //SET1CR 16'h0008
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23'h180003: dout.push_back(rm[ 3]); //SET2CR 16'h000C
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23'h180004: dout.push_back(rm[ 4]); //SET3CR 16'h0010
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23'h180005: dout.push_back(rm[ 5]); //SET4CR 16'h0014
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23'h180006: dout.push_back(rm[ 6]); //SET5CR 16'h0018
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23'h180007: dout.push_back(rm[ 7]); //SET6CR 16'h001C
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23'h180008: dout.push_back(rm[ 8]); //SET7CR 16'h0020
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23'h180009: dout.push_back(rm[ 9]); //SET8CR 16'h0024
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23'h18000a: dout.push_back(rm[10]); //SET9CR 16'h0028
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23'h18000b: dout.push_back(rm[11]); //SET10CR 16'h002C
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23'h18000c: dout.push_back(rm[12]); //SET11CR 16'h0030
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23'h18000d: dout.push_back(rm[13]); //SET12CR 16'h0034
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23'h18000e: dout.push_back(rm[14]); //SET13CR 16'h0038
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23'h18000f: dout.push_back(rm[15]); //SET14CR 16'h003C
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23'h180010: dout.push_back(rm[16]); //SET15CR 16'h0040
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23'h180011: dout.push_back(rm[17]); //DACADDR 16'h0044
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23'h180012: dout.push_back(rm[18]); //DACDW 16'h0048
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23'h180013: dout.push_back(rm[19]); //DACREF 16'h004C
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23'h180014: dout.push_back(rm[20]); //PRBSRST0 16'h0050
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23'h180015: dout.push_back(rm[21]); //PRBSSET0 16'h0054
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23'h180016: dout.push_back(rm[22]); //PRBSRST1 16'h0058
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23'h180017: dout.push_back(rm[23]); //PRBSSET1 16'h005C
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23'h180018: dout.push_back(rm[24]); //PRBSREV 16'h0060
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23'h180019: dout.push_back(rm[25]); //CALSIG 16'h0064
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23'h18001a: dout.push_back(update_rm[26]); //CALEND 16'h0068
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23'h18001b: dout.push_back(rm[27]); //CALRSTN 16'h006C
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23'h18001c: dout.push_back(rm[28]); //CALDIVRSTN 16'h0070
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23'h18001d: dout.push_back(0);
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endcase
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// $display("dout:%h",dout[$]);
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endtask: reg_read
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task dac_refmodel::output_trace(bit[24:0] addr);
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dacreg_trans tr_temp;
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//delay caused by decoder
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@(posedge wif.clk);
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@(negedge wif.clk);
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// @(negedge wif.clk);
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tr_temp = new();
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if(addr[24:20] == 5'h6)
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begin
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tr_temp.Prbs = rm[ 0][0 : 0]; //PRBSCR 16'h0000
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tr_temp.Set0 = rm[ 1][14: 0]; //SET0CR 16'h0004
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tr_temp.Set1 = rm[ 2][14: 0]; //SET1CR 16'h0008
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tr_temp.Set2 = rm[ 3][14: 0]; //SET2CR 16'h000C
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tr_temp.Set3 = rm[ 4][14: 0]; //SET3CR 16'h0010
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tr_temp.Set4 = rm[ 5][14: 0]; //SET4CR 16'h0014
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tr_temp.Set5 = rm[ 6][14: 0]; //SET5CR 16'h0018
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tr_temp.Set6 = rm[ 7][14: 0]; //SET6CR 16'h001C
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tr_temp.Set7 = rm[ 8][14: 0]; //SET7CR 16'h0020
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tr_temp.Set8 = rm[ 9][14: 0]; //SET8CR 16'h0024
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tr_temp.Set9 = rm[10][14: 0]; //SET9CR 16'h0028
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tr_temp.Set10 = rm[11][14: 0]; //SET10CR 16'h002C
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tr_temp.Set11 = rm[12][14: 0]; //SET11CR 16'h0030
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tr_temp.Set12 = rm[13][14: 0]; //SET12CR 16'h0034
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tr_temp.Set13 = rm[14][14: 0]; //SET13CR 16'h0038
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tr_temp.Set14 = rm[15][14: 0]; //SET14CR 16'h003C
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tr_temp.Set15 = rm[16][14: 0]; //SET15CR 16'h0040
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tr_temp.Dac_addr = rm[17][ 2: 0]; //DACADDR 16'h0044
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tr_temp.Dac_dw = rm[18][ 2: 0]; //DACDW 16'h0048
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tr_temp.Dac_ref = rm[19][ 8: 0]; //DACREF 16'h004C
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tr_temp.Prbs_rst0 = rm[20][16: 0]; //PRBSRST0 16'h0050
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tr_temp.Prbs_set0 = rm[21][16: 0]; //PRBSSET0 16'h0054
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tr_temp.Prbs_rst1 = rm[22][16: 0]; //PRBSRST1 16'h0058
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tr_temp.Prbs_set1 = rm[23][16: 0]; //PRBSSET1 16'h005C
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tr_temp.Cal_sig = rm[25][14: 0]; //CALSIG 16'h0060
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tr_temp.Cal_rstn = rm[27][14: 0]; //CALRSTN 16'h006C
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tr_temp.Cal_div_rstn = rm[28][14: 0]; //CALDIVRSTN 16'h0070
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dacout.push_back(tr_temp);
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end
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//$display("addr:%0h",addr);
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//$display("rm[%0h]:%0h",addr[15:2],rm[addr[15:2]]);
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//$display("din:%h",din);
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endtask: output_trace
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