402 lines
13 KiB
Systemverilog
402 lines
13 KiB
Systemverilog
//2024-06-24 linear search for all addr
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class spi_driver;
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static bit my_cmd=1'b0;
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static bit[24:0] last_addr=25'h190_0000;
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static int last_size;
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static bit[24:0] addr_list[$];
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//MOSI data pkt, other input_signals are not packed
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spi_trans m_trans;
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//interface
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virtual spi_if vif;
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//MOSI data_stream input to SPI(DUT)
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bit stream[$];
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//parameter for randomization
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int pktnum;
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int interval;
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int half_sclk;
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bit autarchy;
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rand int error_time;
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constraint cstr{
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error_time <= 544;
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error_time >= -544;
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}
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covergroup SYSAddr;
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coverpoint m_trans.addr{
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bins IDR = {[25'h00:25'h03]};
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bins VIDR = {[25'h04:25'h07]};
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bins DATER = {[25'h08:25'h0B]};
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bins VERR = {[25'h0C:25'h0F]};
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bins TESTR = {[25'h10:25'h13]};
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bins IMR = {[25'h14:25'h17]};
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bins ISR = {[25'h18:25'h1B]};
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bins SFRTR = {[25'h1C:25'h1F]};
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bins SFRR = {[25'h20:25'h23]};
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bins CH0RSTR = {[25'h24:25'h27]};
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bins CH1RSTR = {[25'h28:25'h2B]};
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bins CH2RSTR = {[25'h2C:25'h2F]};
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bins CH3RSTR = {[25'h30:25'h33]};
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bins DBGCFGR = {[25'h34:25'h37]};
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bins MISR = {[25'h40:25'h43]};
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}
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option.per_instance = 1;
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endgroup
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covergroup INSTRAddr;
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coverpoint m_trans.addr{
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bins INSTRCTION[8192] = {[25'h010_0000:25'h010_7FFF]};
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}
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option.per_instance = 1;
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endgroup
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covergroup DATAAddr;
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coverpoint m_trans.addr{
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bins DATA[8192] = {[25'h020_0000:25'h020_7FFF]};
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}
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option.per_instance = 1;
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endgroup
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covergroup CTRAddr;
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coverpoint m_trans.addr{
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bins MCUPARAR0 = {[25'h30_0000:25'h30_0003]};
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bins MCUPARAR1 = {[25'h30_0004:25'h30_0007]};
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bins MCUPARAR2 = {[25'h30_0008:25'h30_000B]};
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bins MCUPARAR3 = {[25'h30_000C:25'h30_000F]};
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bins MCURESR0 = {[25'h30_0010:25'h30_0013]};
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bins MCURESR1 = {[25'h30_0014:25'h30_0017]};
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bins MCURESR2 = {[25'h30_0018:25'h30_001B]};
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bins MCURESR3 = {[25'h30_001C:25'h30_001F]};
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bins RTIMR = {[25'h30_0098:25'h30_009B]};
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bins ICNTR = {[25'h30_009C:25'h30_009F]};
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bins FSIR = {[25'h30_00A0:25'h30_00A3]};
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bins MODMR = {[25'h30_0100:25'h30_0103]};
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bins INTPMR = {[25'h30_0104:25'h30_0107]};
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bins MIXNCOCR = {[25'h30_0108:25'h30_010B]};
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bins MIXNFCWHR = {[25'h30_010C:25'h30_010F]};
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bins MIXNFCWLR = {[25'h30_0110:25'h30_0113]};
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bins MIXNPHAR = {[25'h30_0114:25'h30_0117]};
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bins MIXMR = {[25'h30_0118:25'h30_011B]};
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bins MIXODTR = {[25'h30_011C:25'h30_011F]};
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bins MIXODFR = {[25'h30_0120:25'h30_0123]};
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bins ROLER = {[25'h30_0128:25'h30_012B]};
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bins MIXNCOSCER = {[25'h30_012C:25'h30_012F]};
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bins MODDOTR = {[25'h30_0130:25'h30_0133]};
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bins STR = {[25'h30_0134:25'h30_0137]};
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}
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option.per_instance = 1;
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endgroup
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covergroup ENVELOPEIDAddr;
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coverpoint m_trans.addr{
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bins ENVELOPEID[64] = {[25'h040_0000:25'h040_00FF]};
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}
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option.per_instance = 1;
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endgroup
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covergroup ENVELOPEDATAAddr;
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coverpoint m_trans.addr{
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bins ENVELOPEDATA[8192] = {[25'h050_0000:25'h050_7FFF]};
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}
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option.per_instance = 1;
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endgroup
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covergroup DACAddr;
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coverpoint m_trans.addr{
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bins PRBSCR = {[25'h060_0000:25'h060_0003]};
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bins SET0CR = {[25'h060_0004:25'h060_0007]};
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bins SET1CR = {[25'h060_0008:25'h060_000B]};
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bins SET2CR = {[25'h060_000C:25'h060_000F]};
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bins SET3CR = {[25'h060_0010:25'h060_0013]};
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bins SET4CR = {[25'h060_0014:25'h060_0017]};
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bins SET5CR = {[25'h060_0018:25'h060_001B]};
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bins SET6CR = {[25'h060_001C:25'h060_001F]};
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bins SET7CR = {[25'h060_0020:25'h060_0023]};
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bins SET8CR = {[25'h060_0024:25'h060_0027]};
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bins SET9CR = {[25'h060_0028:25'h060_002B]};
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bins SET10CR = {[25'h060_002C:25'h060_002F]};
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bins SET11CR = {[25'h060_0030:25'h060_0033]};
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bins SET12CR = {[25'h060_0034:25'h060_0037]};
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bins SET13CR = {[25'h060_0038:25'h060_003B]};
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bins SET14CR = {[25'h060_003C:25'h060_003F]};
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bins SET15CR = {[25'h060_0040:25'h060_0043]};
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bins DACADDR = {[25'h060_0044:25'h060_0047]};
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bins DACDW = {[25'h060_0048:25'h060_004B]};
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bins DACREF = {[25'h060_004C:25'h060_004F]};
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bins PRBSRST0 = {[25'h060_0050:25'h060_0053]};
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bins PRBSSET0 = {[25'h060_0054:25'h060_0057]};
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bins PRBSRST1 = {[25'h060_0058:25'h060_005B]};
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bins PRBSSET1 = {[25'h060_005C:25'h060_005F]};
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bins PRBSREV = {[25'h060_0060:25'h060_0063]};
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bins CALSIG = {[25'h060_0064:25'h060_0067]};
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bins CALEND = {[25'h060_0068:25'h060_006B]};
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bins CALRSTN = {[25'h060_006C:25'h060_006F]};
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bins CALDIVRSTN = {[25'h060_0070:25'h060_0073]};
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}
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option.per_instance = 1;
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endgroup
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covergroup MCUAddr;
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coverpoint m_trans.addr{
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bins MCUPARAR0 = {[25'h70_0000:25'h70_0003]};
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bins MCUPARAR1 = {[25'h70_0004:25'h70_0007]};
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bins MCUPARAR2 = {[25'h70_0008:25'h70_000B]};
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bins MCUPARAR3 = {[25'h70_000C:25'h70_000F]};
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bins MCURESR0 = {[25'h70_0010:25'h70_0013]};
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bins MCURESR1 = {[25'h70_0014:25'h70_0017]};
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bins MCURESR2 = {[25'h70_0018:25'h70_001B]};
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bins MCURESR3 = {[25'h70_001C:25'h70_001F]};
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bins CWFR0 = {[25'h70_0040:25'h70_0043]};
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bins CWFR1 = {[25'h70_0044:25'h70_0047]};
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bins CWFR2 = {[25'h70_0048:25'h70_004B]};
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bins CWFR3 = {[25'h70_004C:25'h70_004F]};
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bins CWPRR = {[25'h70_0050:25'h70_0053]};
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bins GAPR0 = {[25'h70_0054:25'h70_0057]};
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bins GAPR1 = {[25'h70_0058:25'h70_005B]};
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bins GAPR2 = {[25'h70_005C:25'h70_005F]};
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bins GAPR3 = {[25'h70_0060:25'h70_0063]};
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bins GAPR4 = {[25'h70_0064:25'h70_0067]};
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bins GAPR5 = {[25'h70_0068:25'h70_006B]};
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bins GAPR6 = {[25'h70_006C:25'h70_006F]};
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bins GAPR7 = {[25'h70_0070:25'h70_0073]};
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bins LCPR = {[25'h70_0074:25'h70_0077]};
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bins AMPR0 = {[25'h70_0078:25'h70_007B]};
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bins AMPR1 = {[25'h70_007C:25'h70_007F]};
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bins AMPR2 = {[25'h70_0080:25'h70_0083]};
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bins AMPR3 = {[25'h70_0084:25'h70_0087]};
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bins BIASR0 = {[25'h70_0088:25'h70_008B]};
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bins BIASR1 = {[25'h70_008C:25'h70_008F]};
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bins BIASR2 = {[25'h70_0090:25'h70_0093]};
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bins BIASR3 = {[25'h70_0094:25'h70_0097]};
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bins RTIMR = {[25'h70_0098:25'h70_009B]};
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bins ICNTR = {[25'h70_009C:25'h70_009F]};
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bins FSIR = {[25'h70_00A0:25'h70_00A3]};
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bins INTPSELR = {[25'h70_00A4:25'h70_00A7]};
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}
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option.per_instance = 1;
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endgroup
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covergroup DBGAddr;
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coverpoint m_trans.addr{
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bins DBGAddr[1024] = {[25'h190_0000:25'h190_0FFF]};
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}
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option.per_instance = 1;
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endgroup
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covergroup PLLAddr;
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coverpoint m_trans.addr{
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bins INTPLL_REFCTRL = {[25'h1f0_0000:25'h1f0_0003]};
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bins INTPLL_PCNT = {[25'h1f0_0004:25'h1f0_0007]};
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bins INTPLL_PFDCTRL = {[25'h1f0_0008:25'h1f0_000B]};
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bins INTPLL_SPDCTRL = {[25'h1f0_000C:25'h1f0_000F]};
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bins INTPLL_PTATCTRL = {[25'h1f0_0010:25'h1f0_0013]};
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bins INTPLL_FLLCTRL = {[25'h1f0_0014:25'h1f0_0017]};
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bins INTPLL_SELCTRL = {[25'h1f0_0018:25'h1f0_001B]};
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bins INTPLL_VCOCTRL = {[25'h1f0_001C:25'h1f0_001F]};
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bins INTPLL_VCOFBADJ = {[25'h1f0_0020:25'h1f0_0023]};
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bins INTPLL_AFCCTRL = {[25'h1f0_0024:25'h1f0_0027]};
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bins INTPLL_AFCCNT = {[25'h1f0_0028:25'h1f0_002B]};
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bins INTPLL_AFCLDCNT = {[25'h1f0_002C:25'h1f0_002F]};
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bins INTPLL_AFCPRES = {[25'h1f0_0030:25'h1f0_0033]};
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bins INTPLL_AFCLDTCC = {[25'h1f0_0034:25'h1f0_0037]};
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bins INTPLL_AFCFBTCC = {[25'h1f0_0038:25'h1f0_003B]};
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bins INTPLL_DIVCFG = {[25'h1f0_003C:25'h1f0_003F]};
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bins INTPLL_TCLKCFG = {[25'h1f0_0040:25'h1f0_0043]};
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bins INTPLL_DCLKSEL = {[25'h1f0_0044:25'h1f0_0047]};
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bins INTPLL_STATUS = {[25'h1f0_0048:25'h1f0_004B]};
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bins INTPLL_SYNCFG = {[25'h1f0_004C:25'h1f0_004F]};
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bins INTPLL_UPDATE = {[25'h1f0_0050:25'h1f0_0053]};
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bins INTPLL_CLKRXPD = {[25'h1f0_0054:25'h1f0_0057]};
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}
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option.per_instance = 1;
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endgroup
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function new();
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SYSAddr = new();
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INSTRAddr = new();
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DATAAddr = new();
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CTRAddr = new();
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ENVELOPEIDAddr = new();
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ENVELOPEDATAAddr = new();
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DACAddr = new();
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MCUAddr = new();
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DBGAddr = new();
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PLLAddr = new();
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endfunction
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extern task do_drive();
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extern task make_pkt(spi_trans tr);
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endclass : spi_driver
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task spi_driver::do_drive();
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int i=0,j=0;
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for(i=0;i<14;i++)
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addr_list[i]=4*i;
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addr_list[14] = 25'h000_0040;
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addr_list.delete(8);
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addr_list.delete(8);
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// $display(addr_list);
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pktnum=addr_list.size()*2;
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$display("pkt_num:\t%0d",pktnum);
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while(!vif.rstn) begin
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vif.csn = 1'b1;
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vif.sclk = 1'b1;
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@(posedge vif.clk);
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end
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for(j=0;j<pktnum;j++) begin
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m_trans = new();
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if(!m_trans.randomize() with {
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cmd==my_cmd;
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(cmd==1'b0 || data.size()==last_size);
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//(cmd==1'b0 || addr==last_addr);
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addr == addr_list[j/2];
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// addr[24:20] == 5'h0 || //sys
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// addr[24:20] == 5'h1 || //instruction srams
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// addr[24:20] == 5'h2 || //data srams
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// addr[24:20] == 5'h3 || //awg
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// addr[24:20] == 5'h4 || //envelope id srams
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// addr[24:20] == 5'h5 || //envelope data srams
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// addr[24:20] == 5'h6 || //dac
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// addr[24:20] == 5'h7 || //mcu
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// addr[24:20] == 5'h19 || //dbg srams
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// addr[24:20] == 5'h1F ; //pll
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addr[24: 20] == 5'h0;
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addr[1:0] == 0;
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// data.size == 2;
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interval == 50;
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})
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$fatal(0,"Randomize Failed");
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if(m_trans.cmd == 1'b0) begin
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last_addr = m_trans.addr;
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last_size = m_trans.data.size();
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end
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my_cmd = ~my_cmd;
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//Autarchy: Testcase force to assign some params
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interval = m_trans.interval;
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if(!autarchy) begin
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half_sclk = m_trans.half_sclk;
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end
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if((m_trans.addr <= 25'h000_001F) &&
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((m_trans.addr + (m_trans.data.size()-1) * 4) >= 25'h000_001C))
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m_trans.data[(25'h000_001C - m_trans.addr)/4] =
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m_trans.data[(25'h000_001C - m_trans.addr)/4] % 4 + 1;
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make_pkt(m_trans);
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//$display(m_trans.addr);
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SYSAddr.sample();
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INSTRAddr.sample();
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DATAAddr.sample();
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CTRAddr.sample();
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ENVELOPEIDAddr.sample();
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ENVELOPEDATAAddr.sample();
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DACAddr.sample();
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MCUAddr.sample();
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DBGAddr.sample();
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PLLAddr.sample();
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repeat(interval)
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@(posedge vif.clk);
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//pktnum--;
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end
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$finish(0);
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//$display(SYSAddr.get_inst_coverage());
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//$display(MCUAddr.get_inst_coverage());
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//$display(AWGAddr.get_inst_coverage());
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endtask : do_drive
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task spi_driver::make_pkt(spi_trans tr);
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int i=0,j=0;
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int cs_time,mo_time;
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//*****************initialize chip_select and input_clk******************//
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vif.csn <= 1'b1;
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vif.sclk <= 1'b1;
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vif.mosi <= stream[0];
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vif.cfgid <= tr.cfgid;
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@(posedge vif.clk);
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vif.csn <= 1'b0;
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vif.sclk <= 1'b1;
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//unpack into bitstream
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stream.delete();
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tr.unpack(stream);
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//mosi valid time: time for bitstream to be all sent
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//csn valid_time: maybe a delay after or ahead of mosi_finished
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mo_time = (stream.size()+1)*2*half_sclk;
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cs_time = (pktnum==1) ? (mo_time + error_time%mo_time) : mo_time;
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//$display("***************************ONE PKT DRIVERED***************************");
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//$display("half_sclk:\t%0d\t\t\t\t\t\t **",half_sclk);
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//$display("interval:\t%0d\t\t\t\t\t\t **",interval);
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//$display("error_time:\t%0d\t\t\t\t\t\t **",error_time);
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//$display("data_size:\t%0d\t\t\t\t\t\t **",tr.data.size());
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//$display("cmd:\t\t%0d\t\t\t\t\t\t **",tr.cmd);
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//$display("id:\t\t%h\t\t\t\t\t\t **",tr.cfgid);
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//$display("addr:\t\t%h\t\t\t\t\t\t **",tr.addr);
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//$display(stream);
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//if(!tr.cmd)
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//for(i=0;i<tr.data.size;i++)
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//$display("mosi:\t\t%h\t\t **",tr.data[i]);
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//********************drive the stream onto interface********************//
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fork
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//************************Make sclk************************//
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begin
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for(j=0;j<cs_time;j++) begin
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if(j % half_sclk == 0 && j!=0)
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vif.sclk <= ~vif.sclk;
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@(posedge vif.clk);
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end
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vif.sclk = 1'b1;
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@(posedge vif.clk);
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vif.csn = 1'b1;
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end
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//************************Send data************************//
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begin
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for(i=0;i<mo_time;i++) begin
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// data will be sampled at posedge,
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// so prepare them at the negedge before each posedge
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if(i % (2*half_sclk) == half_sclk)begin
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vif.mosi <= stream[(i/half_sclk-1)/2];
|
|
//$display(i);
|
|
end
|
|
@(posedge vif.clk);
|
|
end
|
|
end
|
|
|
|
|
|
join
|
|
|
|
//$display("**********************************************************************");
|
|
|
|
endtask
|
|
|