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基于SV的SPI测试平台
1 Commit 1 Branch 0 Tags 98 MiB
Verilog 35.6%
SystemVerilog 28.4%
Assembly 13.6%
Batchfile 13.3%
C 7.4%
Other 1.6%
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thfu af5b47d920 first commit 2024-06-25 16:41:01 +08:00
case1 first commit 2024-06-25 16:41:01 +08:00
case2 first commit 2024-06-25 16:41:01 +08:00
rtl first commit 2024-06-25 16:41:01 +08:00
tb first commit 2024-06-25 16:41:01 +08:00