interface sysreg_if(input clk,input rstn); 

  logic	pll_lock;
  logic	pll_lost_lock;
  logic	ch0_dbg_upd ;
  logic	ch0_dbg_fifo_e;
  logic	ch0_dbg_fifo_f;
  logic	ch0_ldst_addr_unalgn;
  logic	ch0_dec_err;
  logic	ch0_exit_irq ;
  logic	ch1_dbg_upd  ;
  logic	ch1_dbg_fifo_e    ;
  logic	ch1_dbg_fifo_f    ;
  logic	ch1_ldst_addr_unalgn  ;
  logic	ch1_dec_err           ;
  logic	ch1_exit_irq          ;
  logic	ch2_dbg_upd           ;
  logic	ch2_dbg_fifo_e        ;
  logic	ch2_dbg_fifo_f        ;
  logic	ch2_ldst_addr_unalgn  ; 
  logic	ch2_dec_err           ;
  logic	ch2_exit_irq          ;
  logic	ch3_dbg_upd           ; 
  logic	ch3_dbg_fifo_e        ;
  logic	ch3_dbg_fifo_f        ;
  logic	ch3_ldst_addr_unalgn  ;
  logic	ch3_dec_err           ;
  logic	ch3_exit_irq          ;
  logic[3:0]	soft_rstn;
  logic	irq                   ;

  

endinterface : sysreg_if