//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : ssytem_regfile.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 1.0 2022-08-25 PWY //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- // ----------------------------------------------------------- // -- Register address offset macros // ----------------------------------------------------------- //Identity Register `define IDR 16'h00 //Vendor Code Register `define VIDR 16'h04 //RTL Freeze Date Register `define DATER 16'h08 //Version Register `define VERR 16'h0C //Wirte And Read Test Register `define TESTR 16'h10 //Interrupt Mask Register //[31 ] --> PLL LOCK Interrupt Mask //[30 ] --> PLL Lost LOCK Interrupt Mask //[29 ] --> CH3 DBG UPD Interrupt Mask //[28 ] --> CH3 DBG FIFO Empty Interrupt Mask //[27 ] --> CH3 DBG FIFO Full Interrupt Mask //[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask //[25 ] --> CH3 DEC ERR Interrupt Mask //[24 ] --> CH3 EXITI Interrupt Mask //[23:22] --> Reserved //[21 ] --> CH2 DBG UPD Interrupt Mask //[20 ] --> CH2 DBG FIFO Empty Interrupt Mask //[19 ] --> CH2 DBG FIFO Full Interrupt Mask //[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask //[17 ] --> CH2 DEC ERR Interrupt Mask //[16 ] --> CH2 EXITI Interrupt Mask //[15:14] --> Reserved //[13 ] --> CH1 DBG UPD Interrupt Mask //[12 ] --> CH1 DBG FIFO Empty Interrupt Mask //[11 ] --> CH1 DBG FIFO Full Interrupt Mask //[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask //[9 ] --> CH1 DEC ERR Interrupt Mask //[8 ] --> CH1 EXITI Interrupt Mask //[7 :6] --> Reserved //[5 ] --> CH1 DBG UPD Interrupt Mask //[4 ] --> CH1 DBG FIFO Empty Interrupt Mask //[3 ] --> CH1 DBG FIFO Full Interrupt Mask //[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask //[1 ] --> CH1 DEC ERR Interrupt Mask //[0 ] --> CH1 EXITI Interrupt Mask `define IMR 16'h14 //Interrupt Status Register //[31 ] --> PLL LOCK Interrupt Status //[30 ] --> PLL Lost LOCK Interrupt Status //[29 ] --> CH3 DBG UPD Interrupt Status //[28 ] --> CH3 DBG FIFO Empty Interrupt Status //[27 ] --> CH3 DBG FIFO Full Interrupt Status //[26 ] --> CH3 LDST ADDR UNALGN Interrupt Status //[25 ] --> CH3 DEC ERR Interrupt Status //[24 ] --> CH3 EXITI Interrupt Status //[23:22] --> Reserved //[21 ] --> CH2 DBG UPD Interrupt Status //[20 ] --> CH2 DBG FIFO Empty Interrupt Status //[19 ] --> CH2 DBG FIFO Full Interrupt Status //[18 ] --> CH2 LDST ADDR UNALGN Interrupt Status //[17 ] --> CH2 DEC ERR Interrupt Status //[16 ] --> CH2 EXITI Interrupt Status //[15:14] --> Reserved //[13 ] --> CH1 DBG UPD Interrupt Status //[12 ] --> CH1 DBG FIFO Empty Interrupt Status //[11 ] --> CH1 DBG FIFO Full Interrupt Status //[10 ] --> CH1 LDST ADDR UNALGN Interrupt Status //[9 ] --> CH1 DEC ERR Interrupt Status //[8 ] --> CH1 EXITI Interrupt Status //[7 :6] --> Reserved //[5 ] --> CH1 DBG UPD Interrupt Status //[4 ] --> CH1 DBG FIFO Empty Interrupt Status //[3 ] --> CH1 DBG FIFO Full Interrupt Status //[2 ] --> CH1 LDST ADDR UNALGN Interrupt Status //[1 ] --> CH1 DEC ERR Interrupt Status //[0 ] --> CH1 EXITI Interrupt Status `define ISR 16'h18 //Post Masking Interrupt Status Register //Interrupt Status Register //[31 ] --> PLL LOCK Masking Interrupt Status //[30 ] --> PLL Lost LOCK Masking Interrupt Status //[29 ] --> CH3 DBG UPD IMasking Interrupt Status //[28 ] --> CH3 DBG FIFO Empty Masking Interrupt Status //[27 ] --> CH3 DBG FIFO Full Masking Interrupt Status //[26 ] --> CH3 LDST ADDR UNALGN Masking Interrupt Status //[25 ] --> CH3 DEC ERR Masking Interrupt Status //[24 ] --> CH3 EXITI Masking Interrupt Status //[23:22] --> Reserved //[21 ] --> CH2 DBG UPD Masking Interrupt Status //[20 ] --> CH2 DBG FIFO Empty Masking Interrupt Status //[19 ] --> CH2 DBG FIFO Full Masking Interrupt Status //[18 ] --> CH2 LDST ADDR UNALGN Masking Interrupt Status //[17 ] --> CH2 DEC ERR Masking Interrupt Status //[16 ] --> CH2 EXITI Masking Interrupt Status //[15:14] --> Reserved //[13 ] --> CH1 DBG UPD Masking Interrupt Status //[12 ] --> CH1 DBG FIFO Empty Masking Interrupt Status //[11 ] --> CH1 DBG FIFO Full Masking Interrupt Status //[10 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status //[9 ] --> CH1 DEC ERR Masking Interrupt Status //[8 ] --> CH1 EXITI Masking Interrupt Status //[7 :6] --> Reserved //[5 ] --> CH1 DBG UPD Masking Interrupt Status //[4 ] --> CH1 DBG FIFO Empty Masking Interrupt Status //[3 ] --> CH1 DBG FIFO Full Masking Interrupt Status //[2 ] --> CH1 LDST ADDR UNALGN Masking Interrupt Status //[1 ] --> CH1 DEC ERR Masking Interrupt Status //[0 ] --> CH1 EXITI Masking Interrupt Status `define MISR 16'h1C //Soft Reset Time Register `define SFRTR 16'h20 //Soft Reset Register `define SFRR 16'h24 //MCU Soft Reset Register `define MCURSTR 16'h28 //AWG Soft Reset Register `define AWGRSTR 16'h2C //DAC Soft Reset Register `define DACRSTR 16'h30/////////////////////// module system_regfile ( //system port input clk // System Main Clock ,input rst_n // Spi Reset active low //rw op port ,input [31 :0] wrdata // write data ,input wren // write enable ,input [15 :0] rwaddr // read & write address ,input rden // read enable ,output [31 :0] rddata // read data //pll status port ,input pll_lock ,input pll_lost_lock //ch0 status Port ,input ch0_dbg_upd ,input ch0_dbg_fifo_e ,input ch0_dbg_fifo_f ,input ch0_ldst_addr_unalgn ,input ch0_dec_err ,input ch0_exit_irq //ch1 status Port ,input ch1_dbg_upd ,input ch1_dbg_fifo_e ,input ch1_dbg_fifo_f ,input ch1_ldst_addr_unalgn ,input ch1_dec_err ,input ch1_exit_irq //ch2 status Port ,input ch2_dbg_upd ,input ch2_dbg_fifo_e ,input ch2_dbg_fifo_f ,input ch2_ldst_addr_unalgn ,input ch2_dec_err ,input ch2_exit_irq //ch3 status Port ,input ch3_dbg_upd ,input ch3_dbg_fifo_e ,input ch3_dbg_fifo_f ,input ch3_ldst_addr_unalgn ,input ch3_dec_err ,input ch3_exit_irq //Soft Reset out ,output sys_soft_rstn ,output mcu_soft_rstn ,output awg_soft_rstn ,output dac_soft_rstn //Interrupt output port ,output irq ); localparam L = 1'b0, H = 1'b1; localparam IDRD = 32'h41574743; localparam VIDRD = 32'h55535443; localparam DATERD = 32'h20220831; localparam VERSION = 32'h00000001; localparam TESTRD = 32'h01234567; // ------------------------------------------------------ // -- Register enable (select) wires // ------------------------------------------------------ wire idren; // idr select wire vidren; // vidr select wire dateren; // dater select wire verren; // dater select wire testren; // testr select wire imren; // imr select wire isren; // isr select wire misren; // imsr select wire sfrtren; // sfrtr select wire sfrren; // sfrr select wire mcurstren; // mcurstr select wire awgrstren; // awgrstr select wire adacrstren; // adacrstr select // ------------------------------------------------------ // -- Register write enable wires // ------------------------------------------------------ wire testrwe; // testr write enable wire imrwe; // imr write enable wire misrwe; // imsr write enable wire sfrtrwe; // sfrtr write enable wire sfrrwe; // sfrr write enable wire mcurstrwe; // mcurstr write enable wire awgrstrwe; // awgrstr write enable wire adacrstrwe; // adacrstr write enable // ------------------------------------------------------ // -- Misc wires // ------------------------------------------------------ wire [31 :0] irisr ; // original interrupt status wire wire icr ; // interrupt status clear wire // ------------------------------------------------------ // -- Misc Registers // ------------------------------------------------------ reg [31 :0] testr ; reg [31 :0] imr ; reg [31 :0] isr ; reg [31 :0] misr ; reg [31 :0] sfrtr ; reg [0 :0] sfrr ; reg [0 :0] mcurstr ; reg [0 :0] awgrstr ; reg [0 :0] adacrstr ; reg [31 :0] rddata_reg ; reg pll_lock_r ; reg pll_lost_lock_r ; //ch0 status reg reg ch0_dbg_upd_r ; reg ch0_dbg_fifo_e_r ; reg ch0_dbg_fifo_f_r ; reg ch0_ldst_addr_unalgn_r ; reg ch0_dec_err_r ; reg ch0_exit_irq_r ; //ch1 status reg reg ch1_dbg_upd_r ; reg ch1_dbg_fifo_e_r ; reg ch1_dbg_fifo_f_r ; reg ch1_ldst_addr_unalgn_r ; reg ch1_dec_err_r ; reg ch1_exit_irq_r ; //ch2 status reg reg ch2_dbg_upd_r ; reg ch2_dbg_fifo_e_r ; reg ch2_dbg_fifo_f_r ; reg ch2_ldst_addr_unalgn_r ; reg ch2_dec_err_r ; reg ch2_exit_irq_r ; //ch3 status reg reg ch3_dbg_upd_r ; reg ch3_dbg_fifo_e_r ; reg ch3_dbg_fifo_f_r ; reg ch3_ldst_addr_unalgn_r ; reg ch3_dec_err_r ; reg ch3_exit_irq_r ; reg sys_soft_rstn_r ; reg mcu_soft_rstn_r ; reg awg_soft_rstn_r ; reg dac_soft_rstn_r ; // ------------------------------------------------------ // -- Address decoder // // Decodes the register address offset input(reg_addr) // to produce enable (select) signals for each of the // SW-registers in the macrocell. The reg_addr input // is bits [8:0] of the paddr bus. // ------------------------------------------------------ assign idren = (rwaddr[15:2] == `IDR >> 2) ? 1'b1 : 1'b0; assign vidren = (rwaddr[15:2] == `VIDR >> 2) ? 1'b1 : 1'b0; assign dateren = (rwaddr[15:2] == `DATER >> 2) ? 1'b1 : 1'b0; assign testren = (rwaddr[15:2] == `TESTR >> 2) ? 1'b1 : 1'b0; assign imren = (rwaddr[15:2] == `IMR >> 2) ? 1'b1 : 1'b0; assign isren = (rwaddr[15:2] == `ISR >> 2) ? 1'b1 : 1'b0; assign misren = (rwaddr[15:2] == `MISR >> 2) ? 1'b1 : 1'b0; assign sfrtren = (rwaddr[15:2] == `SFRTR >> 2) ? 1'b1 : 1'b0; assign sfrren = (rwaddr[15:2] == `SFRR >> 2) ? 1'b1 : 1'b0; assign mcurstren = (rwaddr[15:2] == `MCURSTR >> 2) ? 1'b1 : 1'b0; assign awgrstren = (rwaddr[15:2] == `AWGRSTR >> 2) ? 1'b1 : 1'b0; assign adacrstren = (rwaddr[15:2] == `DACRSTR >> 2) ? 1'b1 : 1'b0; // ------------------------------------------------------ // -- Write enable signals // // Write enable signals for writable SW-registers. // The write enable for each register is the ANDed // result of the register enable and the input reg_wren // ------------------------------------------------------ assign testrwe = testren & wren; assign imrwe = imren & wren; assign sfrtrwe = sfrtren & wren; assign sfrrwe = sfrren & wren; assign mcurstrwe = mcurstren & wren; assign awgrstrwe = awgrstren & wren; assign adacrstrwe = adacrstren & wren; // --------------------------------------------------------------------------------------------------- // -- interrupt Mask Register // // Write interrupt Mask for 'imr' : 12-bit register // Register is split into the following bit fields // //[31 ] --> PLL LOCK Interrupt Mask //[30 ] --> PLL Lost LOCK Interrupt Mask //[29 ] --> CH3 DBG UPD Interrupt Mask //[28 ] --> CH3 DBG FIFO Empty Interrupt Mask //[27 ] --> CH3 DBG FIFO Full Interrupt Mask //[26 ] --> CH3 LDST ADDR UNALGN Interrupt Mask //[25 ] --> CH3 DEC ERR Interrupt Mask //[24 ] --> CH3 EXITI Interrupt Mask //[23:22] --> Reserved //[21 ] --> CH2 DBG UPD Interrupt Mask //[20 ] --> CH2 DBG FIFO Empty Interrupt Mask //[19 ] --> CH2 DBG FIFO Full Interrupt Mask //[18 ] --> CH2 LDST ADDR UNALGN Interrupt Mask //[17 ] --> CH2 DEC ERR Interrupt Mask //[16 ] --> CH2 EXITI Interrupt Mask //[15:14] --> Reserved //[13 ] --> CH1 DBG UPD Interrupt Mask //[12 ] --> CH1 DBG FIFO Empty Interrupt Mask //[11 ] --> CH1 DBG FIFO Full Interrupt Mask //[10 ] --> CH1 LDST ADDR UNALGN Interrupt Mask //[9 ] --> CH1 DEC ERR Interrupt Mask //[8 ] --> CH1 EXITI Interrupt Mask //[7 :6] --> Reserved //[5 ] --> CH1 DBG UPD Interrupt Mask //[4 ] --> CH1 DBG FIFO Empty Interrupt Mask //[3 ] --> CH1 DBG FIFO Full Interrupt Mask //[2 ] --> CH1 LDST ADDR UNALGN Interrupt Mask //[1 ] --> CH1 DEC ERR Interrupt Mask //[0 ] --> CH1 EXITI Interrupt Mask // --------------------------------------------------------------------------------------------------- sirv_gnrl_dfflr #(32) imr_dfflr (imrwe, wrdata[31:0], imr, clk, rst_n); // ------------------------------------------------------ // -- testr Register // // Write testr for 'TESTR' : 32-bit register // Register is split into the following bit fields // // [31:0] --> testr // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) testr_dfflrd (TESTRD, testrwe, wrdata[31:0], testr, clk, rst_n); // ------------------------------------------------------ // -- Soft Reset Count Register // // Write Soft Reset Count for 'sfrtcr' : 6-bit register // Register is split into the following bit fields // // [31:0] --> sfrtcr,default value 32'd300 // ------------------------------------------------------ sirv_gnrl_dfflrd #(32) sfrtcr_dfflrd (32'd300, sfrtrwe, wrdata[31:0], sfrtr, clk, rst_n);/////////////////////////////sfrtcr-->sfrtr // ------------------------------------------------------ // -- soft reset count // ------------------------------------------------------ reg [31:0] cnt_c; wire add_cnt = (sys_soft_rstn_r == L) | (mcu_soft_rstn_r == L) | (awg_soft_rstn_r == L) | (dac_soft_rstn_r == L); wire end_cnt = add_cnt & (cnt_c == sfrtr-1); wire [31:0] cnt_n = end_cnt ? 32'h0 : add_cnt ? cnt_c + 1'b1 : cnt_c ; sirv_gnrl_dffr #(32) cnt_c_dffr (cnt_n, cnt_c, clk, rst_n); // ------------------------------------------------------ // -- Soft Reset Register // // Write Soft Reset for 'sfrtr' : 1-bit register // Register is split into the following bit fields // // [16'h0024] --> System Soft Reset ,low active // [16'h0028] --> MCU Soft Reset ,low active // [16'h002C] --> AWG Soft Reset ,low active // [16'h0030] --> DAC Soft Reset ,low active // ------------------------------------------------------ //sys_soft_rstn_r wire sys_soft_rstn_en = end_cnt | sfrrwe; wire sys_soft_rstn_w = end_cnt ? 1'b1 : sfrrwe ? 1'b0 : 1'b1 ; sirv_gnrl_dfflrs #(1) sys_soft_rstn_r_dffls (sys_soft_rstn_en, sys_soft_rstn_w, sys_soft_rstn_r, clk, rst_n); //mcu_soft_rstn_r wire mcu_soft_rstn_en = end_cnt | mcurstrwe; wire mcu_soft_rstn_w = end_cnt ? 1'b1 : mcurstrwe ? 1'b0 : 1'b1 ; sirv_gnrl_dfflrs #(1) mcu_soft_rstn_r_dffls (mcu_soft_rstn_en, mcu_soft_rstn_w, mcu_soft_rstn_r, clk, rst_n); //awg_soft_rstn_r wire awg_soft_rstn_en = end_cnt | awgrstrwe; wire awg_soft_rstn_w = end_cnt ? 1'b1 : awgrstrwe ? 1'b0 : 1'b1 ; sirv_gnrl_dfflrs #(1) awg_soft_rstn_r_dffls (awg_soft_rstn_en, awg_soft_rstn_w, awg_soft_rstn_r, clk, rst_n); //dac_soft_rstn_r wire dac_soft_rstn_en = end_cnt | adacrstrwe; wire dac_soft_rstn_w = end_cnt ? 1'b1 : adacrstrwe ? 1'b0 : 1'b1 ; sirv_gnrl_dfflrs #(1) dac_soft_rstn_r_dffls (dac_soft_rstn_en, dac_soft_rstn_w, dac_soft_rstn_r, clk, rst_n); assign sys_soft_rstn = sys_soft_rstn_r;////////////////////////// assign mcu_soft_rstn = mcu_soft_rstn_r;////////////////////////// assign awg_soft_rstn = awg_soft_rstn_r;////////////////////////// assign dac_soft_rstn = dac_soft_rstn_r;////////////////////////// // ------------------------------------------------------ // -- Read data mux // // -- The data from the selected register is // -- placed on a zero-padded 32-bit read data bus. // ------------------------------------------------------ always @(*) begin : RDDATA_PROC rddata_reg = {32{1'b0}}; if(idren == H ) rddata_reg[31:0] = IDRD; if(vidren == H ) rddata_reg[31:0] = VIDRD; if(dateren == H ) rddata_reg[31:0] = DATERD; if(verren == H ) rddata_reg[31:0] = VERSION; if(testren == H ) rddata_reg[31:0] = testr; if(imren == H ) rddata_reg[31:0] = imr; if(isren == H ) rddata_reg[31:0] = isr; if(misren == H ) rddata_reg[31:0] = misr; if(sfrtren == H ) rddata_reg[31:0] = sfrtr; end //rddata sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rst_n); // ------------------------------------------------------ // -- interrupt status // ------------------------------------------------------ //read misr clear interrupts assign icr = (misren) && rden; //pll_lock_r wire pll_lock_en = icr | pll_lock; sirv_gnrl_dfflr #(1) pll_lock_r_dfflr (pll_lock_en, pll_lock, pll_lock_r, clk, rst_n); //pll_lost_lock_r wire pll_lost_lock_en = icr | pll_lock; sirv_gnrl_dfflr #(1) pll_lost_lock_r_dfflr (pll_lost_lock_en, pll_lost_lock, pll_lost_lock_r, clk, rst_n); //ch0_dbg_upd_r wire ch0_dbg_upd_en = icr | ch0_dbg_upd; sirv_gnrl_dfflr #(1) ch0_dbg_upd_r_dfflr (ch0_dbg_upd_en, ch0_dbg_upd, ch0_dbg_upd_r, clk, rst_n); //ch0_dbg_fifo_e_r wire ch0_dbg_fifo_e_en = icr | ch0_dbg_fifo_e; sirv_gnrl_dfflr #(1) ch0_dbg_fifo_e_r_dfflr (ch0_dbg_fifo_e_en, ch0_dbg_fifo_e, ch0_dbg_fifo_e_r, clk, rst_n); //ch0_dbg_fifo_f_r wire ch0_dbg_fifo_f_en = icr | ch0_dbg_fifo_f; sirv_gnrl_dfflr #(1) ch0_dbg_fifo_f_r_dfflr (ch0_dbg_fifo_f_en, ch0_dbg_fifo_f, ch0_dbg_fifo_f_r, clk, rst_n); //ch0_ldst_addr_unalgn_r wire ch0_ldst_addr_unalgn_en = icr | ch0_ldst_addr_unalgn; sirv_gnrl_dfflr #(1) ch0_ldst_addr_unalgn_r_dfflr (ch0_ldst_addr_unalgn_en, ch0_ldst_addr_unalgn, ch0_ldst_addr_unalgn_r, clk, rst_n); //ch0_dec_err_r wire ch0_dec_err_en = icr | ch0_dec_err; sirv_gnrl_dfflr #(1) ch0_dec_err_r_dfflr (ch0_dec_err_en, ch0_dec_err, ch0_dec_err_r, clk, rst_n); //ch0_exit_irq_r wire ch0_exit_irq_en = icr | ch0_exit_irq; sirv_gnrl_dfflr #(1) ch0_exit_irq_r_dfflr (ch0_exit_irq_en, ch0_exit_irq, ch0_exit_irq_r, clk, rst_n); //ch1_dbg_upd_r wire ch1_dbg_upd_en = icr | ch1_dbg_upd; sirv_gnrl_dfflr #(1) ch1_dbg_upd_r_dfflr (ch1_dbg_upd_en, ch1_dbg_upd, ch1_dbg_upd_r, clk, rst_n); //ch1_dbg_fifo_e_r wire ch1_dbg_fifo_e_en = icr | ch1_dbg_fifo_e; sirv_gnrl_dfflr #(1) ch1_dbg_fifo_e_r_dfflr (ch1_dbg_fifo_e_en, ch1_dbg_fifo_e, ch1_dbg_fifo_e_r, clk, rst_n); //ch1_dbg_fifo_f_r wire ch1_dbg_fifo_f_en = icr | ch1_dbg_fifo_f; sirv_gnrl_dfflr #(1) ch1_dbg_fifo_f_r_dfflr (ch1_dbg_fifo_f_en, ch1_dbg_fifo_f, ch1_dbg_fifo_f_r, clk, rst_n); //ch1_ldst_addr_unalgn_r wire ch1_ldst_addr_unalgn_en = icr | ch1_ldst_addr_unalgn; sirv_gnrl_dfflr #(1) ch1_ldst_addr_unalgn_r_dfflr (ch1_ldst_addr_unalgn_en, ch1_ldst_addr_unalgn, ch1_ldst_addr_unalgn_r, clk, rst_n); //ch1_dec_err_r wire ch1_dec_err_en = icr | ch1_dec_err; sirv_gnrl_dfflr #(1) ch1_dec_err_r_dfflr (ch1_dec_err_en, ch1_dec_err, ch1_dec_err_r, clk, rst_n); //ch1_exit_irq_r wire ch1_exit_irq_en = icr | ch1_exit_irq; sirv_gnrl_dfflr #(1) ch1_exit_irq_r_dfflr (ch1_exit_irq_en, ch1_exit_irq, ch1_exit_irq_r, clk, rst_n); //ch2_dbg_upd_r wire ch2_dbg_upd_en = icr | ch2_dbg_upd; sirv_gnrl_dfflr #(1) ch2_dbg_upd_r_dfflr (ch2_dbg_upd_en, ch2_dbg_upd, ch2_dbg_upd_r, clk, rst_n); //ch2_dbg_fifo_e_r wire ch2_dbg_fifo_e_en = icr | ch2_dbg_fifo_e; sirv_gnrl_dfflr #(1) ch2_dbg_fifo_e_r_dfflr (ch2_dbg_fifo_e_en, ch2_dbg_fifo_e, ch2_dbg_fifo_e_r, clk, rst_n); //ch2_dbg_fifo_f_r wire ch2_dbg_fifo_f_en = icr | ch2_dbg_fifo_f; sirv_gnrl_dfflr #(1) ch2_dbg_fifo_f_r_dfflr (ch2_dbg_fifo_f_en, ch2_dbg_fifo_f, ch2_dbg_fifo_f_r, clk, rst_n); //ch2_ldst_addr_unalgn_r wire ch2_ldst_addr_unalgn_en = icr | ch2_ldst_addr_unalgn; sirv_gnrl_dfflr #(1) ch2_ldst_addr_unalgn_r_dfflr (ch2_ldst_addr_unalgn_en, ch2_ldst_addr_unalgn, ch2_ldst_addr_unalgn_r, clk, rst_n); //ch2_dec_err_r wire ch2_dec_err_en = icr | ch2_dec_err; sirv_gnrl_dfflr #(1) ch2_dec_err_r_dfflr (ch2_dec_err_en, ch2_dec_err, ch2_dec_err_r, clk, rst_n); //ch2_exit_irq_r wire ch2_exit_irq_en = icr | ch2_exit_irq; sirv_gnrl_dfflr #(1) ch2_exit_irq_r_dfflr (ch2_exit_irq_en, ch2_exit_irq, ch2_exit_irq_r, clk, rst_n); //ch3_dbg_upd_r wire ch3_dbg_upd_en = icr | ch3_dbg_upd; sirv_gnrl_dfflr #(1) ch3_dbg_upd_r_dfflr (ch3_dbg_upd_en, ch3_dbg_upd, ch3_dbg_upd_r, clk, rst_n); //ch3_dbg_fifo_e_r wire ch3_dbg_fifo_e_en = icr | ch3_dbg_fifo_e; sirv_gnrl_dfflr #(1) ch3_dbg_fifo_e_r_dfflr (ch3_dbg_fifo_e_en, ch3_dbg_fifo_e, ch3_dbg_fifo_e_r, clk, rst_n); //ch3_dbg_fifo_f_r wire ch3_dbg_fifo_f_en = icr | ch3_dbg_fifo_f; sirv_gnrl_dfflr #(1) ch3_dbg_fifo_f_r_dfflr (ch3_dbg_fifo_f_en, ch3_dbg_fifo_f, ch3_dbg_fifo_f_r, clk, rst_n); //ch3_ldst_addr_unalgn_r wire ch3_ldst_addr_unalgn_en = icr | ch3_ldst_addr_unalgn; sirv_gnrl_dfflr #(1) ch3_ldst_addr_unalgn_r_dfflr (ch3_ldst_addr_unalgn_en, ch3_ldst_addr_unalgn, ch3_ldst_addr_unalgn_r, clk, rst_n); //ch3_dec_err_r wire ch3_dec_err_en = icr | ch3_dec_err; sirv_gnrl_dfflr #(1) ch3_dec_err_r_dfflr (ch3_dec_err_en, ch3_dec_err, ch3_dec_err_r, clk, rst_n); //ch3_exit_irq_r wire ch3_exit_irq_en = icr | ch3_exit_irq; sirv_gnrl_dfflr #(1) ch3_exit_irq_r_dfflr (ch3_exit_irq_en, ch3_exit_irq, ch3_exit_irq_r, clk, rst_n); //irisr assign irisr[31] = pll_lock_r ; assign irisr[30] = pll_lost_lock_r ; assign irisr[29] = ch3_dbg_upd_r ; assign irisr[28] = ch3_dbg_fifo_e_r ; assign irisr[27] = ch3_dbg_fifo_f_r ; assign irisr[26] = ch3_ldst_addr_unalgn_r ; assign irisr[25] = ch3_dec_err_r ; assign irisr[24] = ch3_exit_irq_r ; assign irisr[23] = L ; assign irisr[22] = L ; assign irisr[21] = ch2_dbg_upd_r ; assign irisr[20] = ch2_dbg_fifo_e_r ; assign irisr[19] = ch2_dbg_fifo_f_r ; assign irisr[18] = ch2_ldst_addr_unalgn_r ; assign irisr[17] = ch2_dec_err_r ; assign irisr[16] = ch2_exit_irq_r ; assign irisr[15] = L ; assign irisr[14] = L ; assign irisr[13] = ch1_dbg_upd_r ; assign irisr[12] = ch1_dbg_fifo_e_r ; assign irisr[11] = ch1_dbg_fifo_f_r ; assign irisr[10] = ch1_ldst_addr_unalgn_r ; assign irisr[9 ] = ch1_dec_err_r ; assign irisr[8 ] = ch1_exit_irq_r ; assign irisr[7 ] = L ; assign irisr[6 ] = L ; assign irisr[5 ] = ch0_dbg_upd_r ; assign irisr[4 ] = ch0_dbg_fifo_e_r ; assign irisr[3 ] = ch0_dbg_fifo_f_r ; assign irisr[2 ] = ch0_ldst_addr_unalgn_r ; assign irisr[1 ] = ch0_dec_err_r ; assign irisr[0 ] = ch0_exit_irq_r ; // ------------------------------------------------------ // -- Interrupt Status Register - Read Only // // This register contains the status of all // XYZ Chip interrupts after masking. // ------------------------------------------------------ sirv_gnrl_dffr #(32) isr_dffr (irisr, isr, clk, rst_n); //misr wire[31:0] misr_w = imr & irisr; sirv_gnrl_dffr #(32) misr_dffr (misr_w, misr, clk, rst_n); //irq wire irq_w = |misr; sirv_gnrl_dffr #(1) irq_dffr (irq_w, irq, clk, rst_n); endmodule `undef IDR `undef VIDR `undef DATER `undef VERR `undef TESTR `undef IMR `undef ISR `undef MISR `undef SFRTR `undef SFRR `undef MCURSTR `undef AWGRSTR `undef DACRSTR