interface ram_if(input clk, input rst_n);

logic [31 :0] wrdata ;                    // write data
logic         wren   ;                    // write enable
logic [24 :0] rwaddr ;                    // read & write address
logic         rden   ;                    // read enable
logic [31 :0] rddata ;                    // read data

//master
modport m (
   output wrdata 
  ,output wren   
  ,output rwaddr 
  ,output rden   
  ,input  rddata 
);


//slave
modport s (
   input  wrdata 
  ,input  wren   
  ,input  rwaddr 
  ,input  rden   
  ,output rddata 
);

endinterface