interface awgreg_if(input clk,input rstn); 

  //input port
  logic  [2  :0] fb_st_i		;
  logic  [31 :0] run_time		;
  logic  [31 :0] instr_num		;
  logic  [31 :0] mcu_result0            ;   // MCU result 0
  logic  [31 :0] mcu_result1            ;   // MCU result 1
  logic  [31 :0] mcu_result2            ;   // MCU result 2
  logic  [31 :0] mcu_result3            ;   // MCU result 3
 


  //output port
  logic  [31 :0] mcu_param0             ;   // MCU parameter 0
  logic  [31 :0] mcu_param1             ;   // MCU parameter 1
  logic  [31 :0] mcu_param2             ;   // MCU parameter 2
  logic  [31 :0] mcu_param3             ;   // MCU parameter 3
  logic  [2  :0] fb_st_o		;
  logic  	 mod_sel_sideband     	;   //1'b0:Upper sideband;1'b1:Lower sideband;
  logic  	 qam_nco_clr		;
  logic  [47 :0] qam_fcw		;
  logic  [15 :0] qam_pha		;
  logic  [1  :0] qam_mod              	;   //2'b00:bypass;2'b01:mix;2'b10:cos;2'b11:sin;
  logic 	 qam_sel_sideband       ;   //1'b0:Upper sideband;1'b1:Lower sideband;
  logic  [2  :0] intp_mode              ;   //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16;
  logic  [1  :0] intp_sel               ;   //2'b00:HBF;2'b01:Nearest-neighbor interpolator;2'b10:Median interpolator;2'b00:reserve;
  logic  [1  :0] dac_mode_sel           ;   //2'b00:NRZ mode;2'b01:MIX mode;2'b10:2xNRZ mode;2'b00:reserve;
  logic          tc_bypass              ;   //1'b0:bypass;1'b1:enable;
  logic  [31 :0] tcparr0  		;
  logic  [31 :0] tcparr1  		;
  logic  [31 :0] tcparr2  		;
  logic  [31 :0] tcparr3  		;
  logic  [31 :0] tcparr4  		;
  logic  [31 :0] tcparr5  		;
  logic  [31 :0] tcpbrr0    		;
  logic  [31 :0] tcpbrr1  		;
  logic  [31 :0] tcpbrr2  		;
  logic  [31 :0] tcpbrr3  		;
  logic  [31 :0] tcpbrr4  		;
  logic  [31 :0] tcpbrr5  		;
  logic  [31 :0] tcpair0    		;
  logic  [31 :0] tcpair1  		;
  logic  [31 :0] tcpair2  		;
  logic  [31 :0] tcpair3 		;
  logic  [31 :0] tcpair4  		; 
  logic  [31 :0] tcpair5  		;
  logic  [31 :0] tcpbir0    		;
  logic  [31 :0] tcpbir1  		;
  logic  [31 :0] tcpbir2  		;
  logic  [31 :0] tcpbir3  		;
  logic  [31 :0] tcpbir4  		;
  logic  [31 :0] tcpbir5  		;



  

endinterface : awgreg_if