`include "../define/chip_define.v" module TB(); initial begin $fsdbDumpfile("TB1.fsdb"); $fsdbDumpvars(0, TB); $fsdbDumpMDA(); end logic clk; logic rstn; logic clk_rstn; logic qbmcu_i_start; spi_if spi_if(clk,rstn); sysreg_if sys_if(clk,rstn); mcureg_if mcu_if(clk,rstn); awgreg_if awg_if(clk,rstn); pllreg_if pll_if(clk,rstn); dacreg_if dac_if(clk,rstn); initial begin #0; rstn = 1'b0; clk_rstn = 1'b0; clk = 1'b0; qbmcu_i_start = 1'b0; #10; rstn = 1'b1; clk_rstn = 1'b1; end always #0.5 clk = ~clk; reg [31:0] cnt; always@(posedge clk or negedge rstn) if(!rstn) cnt <= 32'd0; else cnt <= cnt + 32'd1; initial begin wait(cnt[31]==1'b1) $finish(0); end wire miso; // Spi Miso wire miso_oen; // Spi Miso output enable assign spi_if.miso = (!U_xyz_chip_top.U_iopad.oen) ? miso : 1'bz; sram_if#(25,32) mst(clk); assign mst.din = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_wrdata; assign mst.wren = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_wren ; assign mst.addr = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rwaddr; assign mst.rden = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rden ; assign mst.dout = U_xyz_chip_top.U_digital_top.U_spi_slave.sys_rddata; //mcu_regfile U2_mcu_regfile ( // .clk ( clk ) // ,.rst_n ( rst_n ) // ,.rwaddr ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].addr[14:0]) // ,.wrdata ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].din ) // ,.wren ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].wren ) // ,.wrmask ( U_xyz_chip_top.U_digital_top.U0_channel_top.preg_o_wrmask ) // ,.rden ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].rden ) // ,.rddata ( U_xyz_chip_top.U_digital_top.U_spi_bus_decoder.slv[7].slave.dout ) // ,.fb_st_info ( U_xyz_chip_top.U_digital_top.U0_channel_top.fb_st_in ) // ,.run_time ( U_xyz_chip_top.U_digital_top.U0_channel_top.run_time ) // ,.instr_num ( U_xyz_chip_top.U_digital_top.U0_channel_top.instr_num ) // ,.mcu_param ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_param ) // ,.mcu_result ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_result ) // ,.mcu_cwfr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_cwfr ) // ,.mcu_gapr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_gapr ) // ,.mcu_ampr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_ampr ) // ,.mcu_baisr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_baisr ) // ,.mcu_nco_pha_clr ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_nco_pha_clr ) // ,.mcu_rz_pha ( U_xyz_chip_top.U_digital_top.U0_channel_top.mcu_rz_pha ) //); `define CH0_FB 2'b10 //////////////////////////////////////////////////////////////////////////////////////// //DUT //////////////////////////////////////////////////////////////////////////////////////// wire async_rstn = rstn; wire por_rstn = 1'b1; logic sync_out ; logic [1 :0] ch0_feedback = `CH0_FB; wire [4 :0] cfgid = 5'b00000; logic irq; //------------------------------PLL cfg pin---------------------------------------------------- logic ref_sel ; // Clock source selection for a frequency divider; // 1'b0:External clock source // 1'b1:internal phase-locked loop clock source logic ref_en ; // Input reference clock enable // 1'b0:enable,1'b1:disable logic ref_s2d_en ; // Referenced clock differential to single-ended conversion enable // 1'b0:enable,1'b1:disable logic [6 :0] p_cnt ; // P counter logic pfd_delay ; // PFD Dead Zone logic pfd_dff_Set ; // Setting the PFD register,active high logic pfd_dff_4and ; // PFD output polarity logic [3 :0] spd_div ; // SPD Frequency Divider logic spd_pulse_width ; // Pulse Width of SPD logic spd_pulse_sw ; // Pulse sw of SPD logic cpc_sel ; // current source selection logic [1 :0] swcp_i ; // PTAT current switch logic [3 :0] sw_ptat_r ; // PTAT current adjustment logic [1 :0] sw_fll_cpi ; // Phase-locked loop charge pump current logic sw_fll_delay ; // PLL Dead Zone logic pfd_sel ; // PFD Loop selection logic spd_sel ; // SPD Loop selection logic fll_sel ; // FLL Loop selection logic vco_tc ; // VCO temperature compensation logic vco_tcr ; // VCO temperature compensation resistor logic vco_gain_adj ; // VCO gain adjustment logic vco_gain_adj_r ; // VCO gain adjustment resistor logic [2 :0] vco_cur_adj ; // VCO current adjustment logic vco_buff_en ; // VCO buff enable,active high logic vco_en ; // VCO enable,active high logic [2 :0] pll_dpwr_adj ; // PLL frequency division output power adjustment logic [6 :0] vco_fb_adj ; // VCO frequency band adjustment logic afc_en ; // AFC enable logic afc_shutdown ; // AFC module shutdown signal logic [0 :0] afc_det_speed ; // AFC detection speed logic [0 :0] flag_out_sel ; // Read and choose the signs logic afc_reset ; // AFC reset logic [10 :0] afc_cnt ; // AFC frequency band adjustment function counter // counting time adjustment logic [10 :0] afc_ld_cnt ; // Adjust the counting time of the AFC lock detection // feature counter logic [3 :0] afc_pres ; // Adjusting the resolution of the AFC comparator logic [14 :0] afc_ld_tcc ; // AFC Lock Detection Function Target Cycle Count logic [14 :0] afc_fb_tcc ; // Target number of cycles for AFC frequency band // adjustment function logic sync_clr ; // PLL div sync clr,low active logic pll_rstn ; // PLL reset,active low logic [0 :0] div_rstn_sel ; // div rstn select, 1'b0: ext clear, 1'b1:inter pll lock logic [1 :0] test_clk_sel ; // test clk select, 2'b00:DIV1 clk, 2'b01:DIV2 clk, 2'b10:DIV4 clk, 2'b11:DIV8 clk logic [0 :0] test_clk_oen ; // test clk output enable, 1'b0:disenable, 1'b1:enable logic [7 :0] dig_clk_sel ; // digital main clk select, one hot code,bit[0]-->0 degree phase,bit[1]-->45 degree phase.....bit[7]-->315degree phae logic clkrx_pdn ; logic pll_lock = 1'b1 ; // PLL LOCK //DAC cfg logic [2 :0] ch0_dac_addr ; logic [2 :0] ch0_dac_dw ; logic [8 :0] ch0_dac_ref ; logic [16 :0] ch0_dac_Prbs_rst0 ; logic [16 :0] ch0_dac_Prbs_set0 ; logic [16 :0] ch0_dac_Prbs_rst1 ; logic [16 :0] ch0_dac_Prbs_set1 ; logic ch0_dac_Cal_sig ; logic ch0_dac_Cal_rstn ; logic ch1_dac_Cal_div_rstn ; logic ch0_dac_Cal_end = 1'b1; //DSP output //`ifdef CHANNEL_XY_ON logic [15 :0] ch0_xy_dsp_dout0 ; logic [15 :0] ch0_xy_dsp_dout1 ; logic [15 :0] ch0_xy_dsp_dout2 ; logic [15 :0] ch0_xy_dsp_dout3 ; logic [15 :0] ch0_xy_dsp_dout4 ; logic [15 :0] ch0_xy_dsp_dout5 ; logic [15 :0] ch0_xy_dsp_dout6 ; logic [15 :0] ch0_xy_dsp_dout7 ; logic [15 :0] ch0_xy_dsp_dout8 ; logic [15 :0] ch0_xy_dsp_dout9 ; logic [15 :0] ch0_xy_dsp_dout10; logic [15 :0] ch0_xy_dsp_dout11; logic [15 :0] ch0_xy_dsp_dout12; logic [15 :0] ch0_xy_dsp_dout13; logic [15 :0] ch0_xy_dsp_dout14; logic [15 :0] ch0_xy_dsp_dout15; //`endif //`ifdef CHANNEL_Z_ON logic [15 :0] ch0_z_dsp_dout0 ; logic [15 :0] ch0_z_dsp_dout1 ; logic [15 :0] ch0_z_dsp_dout2 ; logic [15 :0] ch0_z_dsp_dout3 ; //`endif `ifdef CHANNEL_XY_ON logic [14:0] ch0_xy_A_DEM_MSB_OUT0; logic [14:0] ch0_xy_A_DEM_MSB_OUT1; logic [14:0] ch0_xy_A_DEM_MSB_OUT2; logic [14:0] ch0_xy_A_DEM_MSB_OUT3; logic [14:0] ch0_xy_A_DEM_MSB_OUT4; logic [14:0] ch0_xy_A_DEM_MSB_OUT5; logic [14:0] ch0_xy_A_DEM_MSB_OUT6; logic [14:0] ch0_xy_A_DEM_MSB_OUT7; logic [14:0] ch0_xy_B_DEM_MSB_OUT0; logic [14:0] ch0_xy_B_DEM_MSB_OUT1; logic [14:0] ch0_xy_B_DEM_MSB_OUT2; logic [14:0] ch0_xy_B_DEM_MSB_OUT3; logic [14:0] ch0_xy_B_DEM_MSB_OUT4; logic [14:0] ch0_xy_B_DEM_MSB_OUT5; logic [14:0] ch0_xy_B_DEM_MSB_OUT6; logic [14:0] ch0_xy_B_DEM_MSB_OUT7; logic [6 :0] ch0_xy_A_DEM_ISB_OUT0; logic [6 :0] ch0_xy_A_DEM_ISB_OUT1; logic [6 :0] ch0_xy_A_DEM_ISB_OUT2; logic [6 :0] ch0_xy_A_DEM_ISB_OUT3; logic [6 :0] ch0_xy_A_DEM_ISB_OUT4; logic [6 :0] ch0_xy_A_DEM_ISB_OUT5; logic [6 :0] ch0_xy_A_DEM_ISB_OUT6; logic [6 :0] ch0_xy_A_DEM_ISB_OUT7; logic [6 :0] ch0_xy_B_DEM_ISB_OUT0; logic [6 :0] ch0_xy_B_DEM_ISB_OUT1; logic [6 :0] ch0_xy_B_DEM_ISB_OUT2; logic [6 :0] ch0_xy_B_DEM_ISB_OUT3; logic [6 :0] ch0_xy_B_DEM_ISB_OUT4; logic [6 :0] ch0_xy_B_DEM_ISB_OUT5; logic [6 :0] ch0_xy_B_DEM_ISB_OUT6; logic [6 :0] ch0_xy_B_DEM_ISB_OUT7; logic [8 :0] ch0_xy_A_DEM_LSB_OUT0; logic [8 :0] ch0_xy_A_DEM_LSB_OUT1; logic [8 :0] ch0_xy_A_DEM_LSB_OUT2; logic [8 :0] ch0_xy_A_DEM_LSB_OUT3; logic [8 :0] ch0_xy_A_DEM_LSB_OUT4; logic [8 :0] ch0_xy_A_DEM_LSB_OUT5; logic [8 :0] ch0_xy_A_DEM_LSB_OUT6; logic [8 :0] ch0_xy_A_DEM_LSB_OUT7; logic [8 :0] ch0_xy_B_DEM_LSB_OUT0; logic [8 :0] ch0_xy_B_DEM_LSB_OUT1; logic [8 :0] ch0_xy_B_DEM_LSB_OUT2; logic [8 :0] ch0_xy_B_DEM_LSB_OUT3; logic [8 :0] ch0_xy_B_DEM_LSB_OUT4; logic [8 :0] ch0_xy_B_DEM_LSB_OUT5; logic [8 :0] ch0_xy_B_DEM_LSB_OUT6; logic [8 :0] ch0_xy_B_DEM_LSB_OUT7; `endif `ifdef CHANNEL_Z_ON logic [14 :0] ch0_z_DEM_MSB_OUT0; logic [14 :0] ch0_z_DEM_MSB_OUT1; logic [14 :0] ch0_z_DEM_MSB_OUT2; logic [14 :0] ch0_z_DEM_MSB_OUT3; logic [6 :0] ch0_z_DEM_ISB_OUT0; logic [6 :0] ch0_z_DEM_ISB_OUT1; logic [6 :0] ch0_z_DEM_ISB_OUT2; logic [6 :0] ch0_z_DEM_ISB_OUT3; logic [8 :0] ch0_z_DEM_LSB_OUT0; logic [8 :0] ch0_z_DEM_LSB_OUT1; logic [8 :0] ch0_z_DEM_LSB_OUT2; logic [8 :0] ch0_z_DEM_LSB_OUT3; `endif //////////////////////////////////////////////////////////////////////////////////////////////////// xyz_chip_top U_xyz_chip_top ( .clk ( clk ) ,.por_rstn ( por_rstn ) ,.PI_async_rstn ( async_rstn ) ,.PI_sync_in ( qbmcu_i_start ) ,.PO_sync_out ( sync_out ) ,.PI_ch0_feedback ( ch0_feedback ) `ifdef CHANNEL_IS_FOUR ,.PI_ch1_feedback ( ch1_feedback ) ,.PI_ch2_feedback ( ch2_feedback ) ,.PI_ch3_feedback ( ch3_feedback ) `endif ,.PI_cfgid ( spi_if.cfgid ) ,.PI_sclk ( spi_if.sclk ) ,.PI_csn ( spi_if.csn ) ,.PI_mosi ( spi_if.mosi ) ,.PO_miso ( miso ) ,.PO_irq ( irq ) ,.ref_sel ( ref_sel ) ,.ref_en ( ref_en ) ,.ref_s2d_en ( ref_s2d_en ) ,.p_cnt ( p_cnt ) ,.pfd_delay ( pfd_delay ) ,.pfd_dff_Set ( pfd_dff_Set ) ,.pfd_dff_4and ( pfd_dff_4and ) ,.spd_div ( spd_div ) ,.spd_pulse_width ( spd_pulse_width ) ,.spd_pulse_sw ( spd_pulse_sw ) ,.cpc_sel ( cpc_sel ) ,.swcp_i ( swcp_i ) ,.sw_ptat_r ( sw_ptat_r ) ,.sw_fll_cpi ( sw_fll_cpi ) ,.sw_fll_delay ( sw_fll_delay ) ,.pfd_sel ( pfd_sel ) ,.spd_sel ( spd_sel ) ,.fll_sel ( fll_sel ) ,.vco_tc ( vco_tc ) ,.vco_tcr ( vco_tcr ) ,.vco_gain_adj ( vco_gain_adj ) ,.vco_gain_adj_r ( vco_gain_adj_r ) ,.vco_cur_adj ( vco_cur_adj ) ,.vco_buff_en ( vco_buff_en ) ,.vco_en ( vco_en ) ,.pll_dpwr_adj ( pll_dpwr_adj ) ,.vco_fb_adj ( vco_fb_adj ) ,.afc_en ( afc_en ) ,.afc_shutdown ( afc_shutdown ) ,.afc_det_speed ( afc_det_speed ) ,.flag_out_sel ( flag_out_sel ) ,.afc_reset ( afc_reset ) ,.afc_cnt ( afc_cnt ) ,.afc_ld_cnt ( afc_ld_cnt ) ,.afc_pres ( afc_pres ) ,.afc_ld_tcc ( afc_ld_tcc ) ,.afc_fb_tcc ( afc_fb_tcc ) ,.sync_clr ( sync_clr ) ,.pll_rstn ( pll_rstn ) ,.div_rstn_sel ( div_rstn_sel ) ,.test_clk_sel ( test_clk_sel ) ,.test_clk_oen ( test_clk_oen ) ,.dig_clk_sel ( dig_clk_sel ) ,.clkrx_pdn ( clkrx_pdn ) ,.pll_lock ( pll_lock ) ,.ch0_dac_addr ( ch0_dac_addr ) ,.ch0_dac_dw ( ch0_dac_dw ) ,.ch0_dac_ref ( ch0_dac_ref ) ,.ch0_dac_Prbs_rst0 ( ch0_dac_Prbs_rst0 ) ,.ch0_dac_Prbs_set0 ( ch0_dac_Prbs_set0 ) ,.ch0_dac_Prbs_rst1 ( ch0_dac_Prbs_rst1 ) ,.ch0_dac_Prbs_set1 ( ch0_dac_Prbs_set1 ) ,.ch0_dac_Cal_sig ( ch0_dac_Cal_sig ) ,.ch0_dac_Cal_rstn ( ch0_dac_Cal_rstn ) ,.ch0_dac_Cal_div_rstn ( ch0_dac_Cal_div_rstn ) ,.ch0_dac_Cal_end ( ch0_dac_Cal_end ) `ifdef CHANNEL_IS_FOUR ,.ch1_dac_addr ( ch1_dac_addr ) ,.ch1_dac_dw ( ch1_dac_dw ) ,.ch1_dac_ref ( ch1_dac_ref ) ,.ch1_dac_Prbs_rst0 ( ch1_dac_Prbs_rst0 ) ,.ch1_dac_Prbs_set0 ( ch1_dac_Prbs_set0 ) ,.ch1_dac_Prbs_rst1 ( ch1_dac_Prbs_rst1 ) ,.ch1_dac_Prbs_set1 ( ch1_dac_Prbs_set1 ) ,.ch1_dac_Cal_sig ( ch1_dac_Cal_sig ) ,.ch1_dac_Cal_rstn ( ch1_dac_Cal_rstn ) ,.ch1_dac_Cal_div_rstn ( ch1_dac_Cal_div_rstn ) ,.ch1_dac_Cal_end ( ch1_dac_Cal_end ) ,.ch2_dac_addr ( ch2_dac_addr ) ,.ch2_dac_dw ( ch2_dac_dw ) ,.ch2_dac_ref ( ch2_dac_ref ) ,.ch2_dac_Prbs_rst0 ( ch2_dac_Prbs_rst0 ) ,.ch2_dac_Prbs_set0 ( ch2_dac_Prbs_set0 ) ,.ch2_dac_Prbs_rst1 ( ch2_dac_Prbs_rst1 ) ,.ch2_dac_Prbs_set1 ( ch2_dac_Prbs_set1 ) ,.ch2_dac_Cal_sig ( ch2_dac_Cal_sig ) ,.ch2_dac_Cal_rstn ( ch2_dac_Cal_rstn ) ,.ch2_dac_Cal_div_rstn ( ch2_dac_Cal_div_rstn ) ,.ch2_dac_Cal_end ( ch2_dac_Cal_end ) ,.ch3_dac_dw ( ch3_dac_dw ) ,.ch3_dac_ref ( ch3_dac_ref ) ,.ch3_dac_Prbs_rst0 ( ch3_dac_Prbs_rst0 ) ,.ch3_dac_Prbs_set0 ( ch3_dac_Prbs_set0 ) ,.ch3_dac_Prbs_rst1 ( ch3_dac_Prbs_rst1 ) ,.ch3_dac_Prbs_set1 ( ch3_dac_Prbs_set1 ) ,.ch3_dac_Cal_sig ( ch3_dac_Cal_sig ) ,.ch3_dac_Cal_rstn ( ch3_dac_Cal_rstn ) ,.ch0_dac_Cal_div_rstn ( ch3_dac_Cal_div_rstn ) ,.ch3_dac_Cal_end ( ch3_dac_Cal_end ) `endif //------------------------------Ch0 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,.ch0_xy_A_DEM_MSB_OUT0 ( ch0_xy_A_DEM_MSB_OUT0 ) ,.ch0_xy_A_DEM_MSB_OUT1 ( ch0_xy_A_DEM_MSB_OUT1 ) ,.ch0_xy_A_DEM_MSB_OUT2 ( ch0_xy_A_DEM_MSB_OUT2 ) ,.ch0_xy_A_DEM_MSB_OUT3 ( ch0_xy_A_DEM_MSB_OUT3 ) ,.ch0_xy_A_DEM_MSB_OUT4 ( ch0_xy_A_DEM_MSB_OUT4 ) ,.ch0_xy_A_DEM_MSB_OUT5 ( ch0_xy_A_DEM_MSB_OUT5 ) ,.ch0_xy_A_DEM_MSB_OUT6 ( ch0_xy_A_DEM_MSB_OUT6 ) ,.ch0_xy_A_DEM_MSB_OUT7 ( ch0_xy_A_DEM_MSB_OUT7 ) ,.ch0_xy_B_DEM_MSB_OUT0 ( ch0_xy_B_DEM_MSB_OUT0 ) ,.ch0_xy_B_DEM_MSB_OUT1 ( ch0_xy_B_DEM_MSB_OUT1 ) ,.ch0_xy_B_DEM_MSB_OUT2 ( ch0_xy_B_DEM_MSB_OUT2 ) ,.ch0_xy_B_DEM_MSB_OUT3 ( ch0_xy_B_DEM_MSB_OUT3 ) ,.ch0_xy_B_DEM_MSB_OUT4 ( ch0_xy_B_DEM_MSB_OUT4 ) ,.ch0_xy_B_DEM_MSB_OUT5 ( ch0_xy_B_DEM_MSB_OUT5 ) ,.ch0_xy_B_DEM_MSB_OUT6 ( ch0_xy_B_DEM_MSB_OUT6 ) ,.ch0_xy_B_DEM_MSB_OUT7 ( ch0_xy_B_DEM_MSB_OUT7 ) ,.ch0_xy_A_DEM_ISB_OUT0 ( ch0_xy_A_DEM_ISB_OUT0 ) ,.ch0_xy_A_DEM_ISB_OUT1 ( ch0_xy_A_DEM_ISB_OUT1 ) ,.ch0_xy_A_DEM_ISB_OUT2 ( ch0_xy_A_DEM_ISB_OUT2 ) ,.ch0_xy_A_DEM_ISB_OUT3 ( ch0_xy_A_DEM_ISB_OUT3 ) ,.ch0_xy_A_DEM_ISB_OUT4 ( ch0_xy_A_DEM_ISB_OUT4 ) ,.ch0_xy_A_DEM_ISB_OUT5 ( ch0_xy_A_DEM_ISB_OUT5 ) ,.ch0_xy_A_DEM_ISB_OUT6 ( ch0_xy_A_DEM_ISB_OUT6 ) ,.ch0_xy_A_DEM_ISB_OUT7 ( ch0_xy_A_DEM_ISB_OUT7 ) ,.ch0_xy_B_DEM_ISB_OUT0 ( ch0_xy_B_DEM_ISB_OUT0 ) ,.ch0_xy_B_DEM_ISB_OUT1 ( ch0_xy_B_DEM_ISB_OUT1 ) ,.ch0_xy_B_DEM_ISB_OUT2 ( ch0_xy_B_DEM_ISB_OUT2 ) ,.ch0_xy_B_DEM_ISB_OUT3 ( ch0_xy_B_DEM_ISB_OUT3 ) ,.ch0_xy_B_DEM_ISB_OUT4 ( ch0_xy_B_DEM_ISB_OUT4 ) ,.ch0_xy_B_DEM_ISB_OUT5 ( ch0_xy_B_DEM_ISB_OUT5 ) ,.ch0_xy_B_DEM_ISB_OUT6 ( ch0_xy_B_DEM_ISB_OUT6 ) ,.ch0_xy_B_DEM_ISB_OUT7 ( ch0_xy_B_DEM_ISB_OUT7 ) ,.ch0_xy_A_DEM_LSB_OUT0 ( ch0_xy_A_DEM_LSB_OUT0 ) ,.ch0_xy_A_DEM_LSB_OUT1 ( ch0_xy_A_DEM_LSB_OUT1 ) ,.ch0_xy_A_DEM_LSB_OUT2 ( ch0_xy_A_DEM_LSB_OUT2 ) ,.ch0_xy_A_DEM_LSB_OUT3 ( ch0_xy_A_DEM_LSB_OUT3 ) ,.ch0_xy_A_DEM_LSB_OUT4 ( ch0_xy_A_DEM_LSB_OUT4 ) ,.ch0_xy_A_DEM_LSB_OUT5 ( ch0_xy_A_DEM_LSB_OUT5 ) ,.ch0_xy_A_DEM_LSB_OUT6 ( ch0_xy_A_DEM_LSB_OUT6 ) ,.ch0_xy_A_DEM_LSB_OUT7 ( ch0_xy_A_DEM_LSB_OUT7 ) ,.ch0_xy_B_DEM_LSB_OUT0 ( ch0_xy_B_DEM_LSB_OUT0 ) ,.ch0_xy_B_DEM_LSB_OUT1 ( ch0_xy_B_DEM_LSB_OUT1 ) ,.ch0_xy_B_DEM_LSB_OUT2 ( ch0_xy_B_DEM_LSB_OUT2 ) ,.ch0_xy_B_DEM_LSB_OUT3 ( ch0_xy_B_DEM_LSB_OUT3 ) ,.ch0_xy_B_DEM_LSB_OUT4 ( ch0_xy_B_DEM_LSB_OUT4 ) ,.ch0_xy_B_DEM_LSB_OUT5 ( ch0_xy_B_DEM_LSB_OUT5 ) ,.ch0_xy_B_DEM_LSB_OUT6 ( ch0_xy_B_DEM_LSB_OUT6 ) ,.ch0_xy_B_DEM_LSB_OUT7 ( ch0_xy_B_DEM_LSB_OUT7 ) `endif `ifdef CHANNEL_Z_ON ,.ch0_z_DEM_MSB_OUT0 ( ch0_z_DEM_MSB_OUT0 ) ,.ch0_z_DEM_MSB_OUT1 ( ch0_z_DEM_MSB_OUT1 ) ,.ch0_z_DEM_MSB_OUT2 ( ch0_z_DEM_MSB_OUT2 ) ,.ch0_z_DEM_MSB_OUT3 ( ch0_z_DEM_MSB_OUT3 ) ,.ch0_z_DEM_ISB_OUT0 ( ch0_z_DEM_ISB_OUT0 ) ,.ch0_z_DEM_ISB_OUT1 ( ch0_z_DEM_ISB_OUT1 ) ,.ch0_z_DEM_ISB_OUT2 ( ch0_z_DEM_ISB_OUT2 ) ,.ch0_z_DEM_ISB_OUT3 ( ch0_z_DEM_ISB_OUT3 ) ,.ch0_z_DEM_LSB_OUT0 ( ch0_z_DEM_LSB_OUT0 ) ,.ch0_z_DEM_LSB_OUT1 ( ch0_z_DEM_LSB_OUT1 ) ,.ch0_z_DEM_LSB_OUT2 ( ch0_z_DEM_LSB_OUT2 ) ,.ch0_z_DEM_LSB_OUT3 ( ch0_z_DEM_LSB_OUT3 ) `endif `ifdef CHANNEL_IS_FOUR //------------------------------Ch1 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,.ch1_xy_A_DEM_MSB_OUT0 ( ch1_xy_A_DEM_MSB_OUT0 ) ,.ch1_xy_A_DEM_MSB_OUT1 ( ch1_xy_A_DEM_MSB_OUT1 ) ,.ch1_xy_A_DEM_MSB_OUT2 ( ch1_xy_A_DEM_MSB_OUT2 ) ,.ch1_xy_A_DEM_MSB_OUT3 ( ch1_xy_A_DEM_MSB_OUT3 ) ,.ch1_xy_A_DEM_MSB_OUT4 ( ch1_xy_A_DEM_MSB_OUT4 ) ,.ch1_xy_A_DEM_MSB_OUT5 ( ch1_xy_A_DEM_MSB_OUT5 ) ,.ch1_xy_A_DEM_MSB_OUT6 ( ch1_xy_A_DEM_MSB_OUT6 ) ,.ch1_xy_A_DEM_MSB_OUT7 ( ch1_xy_A_DEM_MSB_OUT7 ) ,.ch1_xy_B_DEM_MSB_OUT0 ( ch1_xy_B_DEM_MSB_OUT0 ) ,.ch1_xy_B_DEM_MSB_OUT1 ( ch1_xy_B_DEM_MSB_OUT1 ) ,.ch1_xy_B_DEM_MSB_OUT2 ( ch1_xy_B_DEM_MSB_OUT2 ) ,.ch1_xy_B_DEM_MSB_OUT3 ( ch1_xy_B_DEM_MSB_OUT3 ) ,.ch1_xy_B_DEM_MSB_OUT4 ( ch1_xy_B_DEM_MSB_OUT4 ) ,.ch1_xy_B_DEM_MSB_OUT5 ( ch1_xy_B_DEM_MSB_OUT5 ) ,.ch1_xy_B_DEM_MSB_OUT6 ( ch1_xy_B_DEM_MSB_OUT6 ) ,.ch1_xy_B_DEM_MSB_OUT7 ( ch1_xy_B_DEM_MSB_OUT7 ) ,.ch1_xy_A_DEM_ISB_OUT0 ( ch1_xy_A_DEM_ISB_OUT0 ) ,.ch1_xy_A_DEM_ISB_OUT1 ( ch1_xy_A_DEM_ISB_OUT1 ) ,.ch1_xy_A_DEM_ISB_OUT2 ( ch1_xy_A_DEM_ISB_OUT2 ) ,.ch1_xy_A_DEM_ISB_OUT3 ( ch1_xy_A_DEM_ISB_OUT3 ) ,.ch1_xy_A_DEM_ISB_OUT4 ( ch1_xy_A_DEM_ISB_OUT4 ) ,.ch1_xy_A_DEM_ISB_OUT5 ( ch1_xy_A_DEM_ISB_OUT5 ) ,.ch1_xy_A_DEM_ISB_OUT6 ( ch1_xy_A_DEM_ISB_OUT6 ) ,.ch1_xy_A_DEM_ISB_OUT7 ( ch1_xy_A_DEM_ISB_OUT7 ) ,.ch1_xy_B_DEM_ISB_OUT0 ( ch1_xy_B_DEM_ISB_OUT0 ) ,.ch1_xy_B_DEM_ISB_OUT1 ( ch1_xy_B_DEM_ISB_OUT1 ) ,.ch1_xy_B_DEM_ISB_OUT2 ( ch1_xy_B_DEM_ISB_OUT2 ) ,.ch1_xy_B_DEM_ISB_OUT3 ( ch1_xy_B_DEM_ISB_OUT3 ) ,.ch1_xy_B_DEM_ISB_OUT4 ( ch1_xy_B_DEM_ISB_OUT4 ) ,.ch1_xy_B_DEM_ISB_OUT5 ( ch1_xy_B_DEM_ISB_OUT5 ) ,.ch1_xy_B_DEM_ISB_OUT6 ( ch1_xy_B_DEM_ISB_OUT6 ) ,.ch1_xy_B_DEM_ISB_OUT7 ( ch1_xy_B_DEM_ISB_OUT7 ) ,.ch1_xy_A_DEM_LSB_OUT0 ( ch1_xy_A_DEM_LSB_OUT0 ) ,.ch1_xy_A_DEM_LSB_OUT1 ( ch1_xy_A_DEM_LSB_OUT1 ) ,.ch1_xy_A_DEM_LSB_OUT2 ( ch1_xy_A_DEM_LSB_OUT2 ) ,.ch1_xy_A_DEM_LSB_OUT3 ( ch1_xy_A_DEM_LSB_OUT3 ) ,.ch1_xy_A_DEM_LSB_OUT4 ( ch1_xy_A_DEM_LSB_OUT4 ) ,.ch1_xy_A_DEM_LSB_OUT5 ( ch1_xy_A_DEM_LSB_OUT5 ) ,.ch1_xy_A_DEM_LSB_OUT6 ( ch1_xy_A_DEM_LSB_OUT6 ) ,.ch1_xy_A_DEM_LSB_OUT7 ( ch1_xy_A_DEM_LSB_OUT7 ) ,.ch1_xy_B_DEM_LSB_OUT0 ( ch1_xy_B_DEM_LSB_OUT0 ) ,.ch1_xy_B_DEM_LSB_OUT1 ( ch1_xy_B_DEM_LSB_OUT1 ) ,.ch1_xy_B_DEM_LSB_OUT2 ( ch1_xy_B_DEM_LSB_OUT2 ) ,.ch1_xy_B_DEM_LSB_OUT3 ( ch1_xy_B_DEM_LSB_OUT3 ) ,.ch1_xy_B_DEM_LSB_OUT4 ( ch1_xy_B_DEM_LSB_OUT4 ) ,.ch1_xy_B_DEM_LSB_OUT5 ( ch1_xy_B_DEM_LSB_OUT5 ) ,.ch1_xy_B_DEM_LSB_OUT6 ( ch1_xy_B_DEM_LSB_OUT6 ) ,.ch1_xy_B_DEM_LSB_OUT7 ( ch1_xy_B_DEM_LSB_OUT7 ) `endif `ifdef CHANNEL_Z_ON ,.ch1_z_DEM_MSB_OUT0 ( ch1_z_DEM_MSB_OUT0 ) ,.ch1_z_DEM_MSB_OUT1 ( ch1_z_DEM_MSB_OUT1 ) ,.ch1_z_DEM_MSB_OUT2 ( ch1_z_DEM_MSB_OUT2 ) ,.ch1_z_DEM_MSB_OUT3 ( ch1_z_DEM_MSB_OUT3 ) ,.ch1_z_DEM_ISB_OUT0 ( ch1_z_DEM_ISB_OUT0 ) ,.ch1_z_DEM_ISB_OUT1 ( ch1_z_DEM_ISB_OUT1 ) ,.ch1_z_DEM_ISB_OUT2 ( ch1_z_DEM_ISB_OUT2 ) ,.ch1_z_DEM_ISB_OUT3 ( ch1_z_DEM_ISB_OUT3 ) ,.ch1_z_DEM_LSB_OUT0 ( ch1_z_DEM_LSB_OUT0 ) ,.ch1_z_DEM_LSB_OUT1 ( ch1_z_DEM_LSB_OUT1 ) ,.ch1_z_DEM_LSB_OUT2 ( ch1_z_DEM_LSB_OUT2 ) ,.ch1_z_DEM_LSB_OUT3 ( ch1_z_DEM_LSB_OUT3 ) `endif //------------------------------Ch2 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,.ch2_xy_A_DEM_MSB_OUT0 ( ch2_xy_A_DEM_MSB_OUT0 ) ,.ch2_xy_A_DEM_MSB_OUT1 ( ch2_xy_A_DEM_MSB_OUT1 ) ,.ch2_xy_A_DEM_MSB_OUT2 ( ch2_xy_A_DEM_MSB_OUT2 ) ,.ch2_xy_A_DEM_MSB_OUT3 ( ch2_xy_A_DEM_MSB_OUT3 ) ,.ch2_xy_A_DEM_MSB_OUT4 ( ch2_xy_A_DEM_MSB_OUT4 ) ,.ch2_xy_A_DEM_MSB_OUT5 ( ch2_xy_A_DEM_MSB_OUT5 ) ,.ch2_xy_A_DEM_MSB_OUT6 ( ch2_xy_A_DEM_MSB_OUT6 ) ,.ch2_xy_A_DEM_MSB_OUT7 ( ch2_xy_A_DEM_MSB_OUT7 ) ,.ch2_xy_B_DEM_MSB_OUT0 ( ch2_xy_B_DEM_MSB_OUT0 ) ,.ch2_xy_B_DEM_MSB_OUT1 ( ch2_xy_B_DEM_MSB_OUT1 ) ,.ch2_xy_B_DEM_MSB_OUT2 ( ch2_xy_B_DEM_MSB_OUT2 ) ,.ch2_xy_B_DEM_MSB_OUT3 ( ch2_xy_B_DEM_MSB_OUT3 ) ,.ch2_xy_B_DEM_MSB_OUT4 ( ch2_xy_B_DEM_MSB_OUT4 ) ,.ch2_xy_B_DEM_MSB_OUT5 ( ch2_xy_B_DEM_MSB_OUT5 ) ,.ch2_xy_B_DEM_MSB_OUT6 ( ch2_xy_B_DEM_MSB_OUT6 ) ,.ch2_xy_B_DEM_MSB_OUT7 ( ch2_xy_B_DEM_MSB_OUT7 ) ,.ch2_xy_A_DEM_ISB_OUT0 ( ch2_xy_A_DEM_ISB_OUT0 ) ,.ch2_xy_A_DEM_ISB_OUT1 ( ch2_xy_A_DEM_ISB_OUT1 ) ,.ch2_xy_A_DEM_ISB_OUT2 ( ch2_xy_A_DEM_ISB_OUT2 ) ,.ch2_xy_A_DEM_ISB_OUT3 ( ch2_xy_A_DEM_ISB_OUT3 ) ,.ch2_xy_A_DEM_ISB_OUT4 ( ch2_xy_A_DEM_ISB_OUT4 ) ,.ch2_xy_A_DEM_ISB_OUT5 ( ch2_xy_A_DEM_ISB_OUT5 ) ,.ch2_xy_A_DEM_ISB_OUT6 ( ch2_xy_A_DEM_ISB_OUT6 ) ,.ch2_xy_A_DEM_ISB_OUT7 ( ch2_xy_A_DEM_ISB_OUT7 ) ,.ch2_xy_B_DEM_ISB_OUT0 ( ch2_xy_B_DEM_ISB_OUT0 ) ,.ch2_xy_B_DEM_ISB_OUT1 ( ch2_xy_B_DEM_ISB_OUT1 ) ,.ch2_xy_B_DEM_ISB_OUT2 ( ch2_xy_B_DEM_ISB_OUT2 ) ,.ch2_xy_B_DEM_ISB_OUT3 ( ch2_xy_B_DEM_ISB_OUT3 ) ,.ch2_xy_B_DEM_ISB_OUT4 ( ch2_xy_B_DEM_ISB_OUT4 ) ,.ch2_xy_B_DEM_ISB_OUT5 ( ch2_xy_B_DEM_ISB_OUT5 ) ,.ch2_xy_B_DEM_ISB_OUT6 ( ch2_xy_B_DEM_ISB_OUT6 ) ,.ch2_xy_B_DEM_ISB_OUT7 ( ch2_xy_B_DEM_ISB_OUT7 ) ,.ch2_xy_A_DEM_LSB_OUT0 ( ch2_xy_A_DEM_LSB_OUT0 ) ,.ch2_xy_A_DEM_LSB_OUT1 ( ch2_xy_A_DEM_LSB_OUT1 ) ,.ch2_xy_A_DEM_LSB_OUT2 ( ch2_xy_A_DEM_LSB_OUT2 ) ,.ch2_xy_A_DEM_LSB_OUT3 ( ch2_xy_A_DEM_LSB_OUT3 ) ,.ch2_xy_A_DEM_LSB_OUT4 ( ch2_xy_A_DEM_LSB_OUT4 ) ,.ch2_xy_A_DEM_LSB_OUT5 ( ch2_xy_A_DEM_LSB_OUT5 ) ,.ch2_xy_A_DEM_LSB_OUT6 ( ch2_xy_A_DEM_LSB_OUT6 ) ,.ch2_xy_A_DEM_LSB_OUT7 ( ch2_xy_A_DEM_LSB_OUT7 ) ,.ch2_xy_B_DEM_LSB_OUT0 ( ch2_xy_B_DEM_LSB_OUT0 ) ,.ch2_xy_B_DEM_LSB_OUT1 ( ch2_xy_B_DEM_LSB_OUT1 ) ,.ch2_xy_B_DEM_LSB_OUT2 ( ch2_xy_B_DEM_LSB_OUT2 ) ,.ch2_xy_B_DEM_LSB_OUT3 ( ch2_xy_B_DEM_LSB_OUT3 ) ,.ch2_xy_B_DEM_LSB_OUT4 ( ch2_xy_B_DEM_LSB_OUT4 ) ,.ch2_xy_B_DEM_LSB_OUT5 ( ch2_xy_B_DEM_LSB_OUT5 ) ,.ch2_xy_B_DEM_LSB_OUT6 ( ch2_xy_B_DEM_LSB_OUT6 ) ,.ch2_xy_B_DEM_LSB_OUT7 ( ch2_xy_B_DEM_LSB_OUT7 ) `endif `ifdef CHANNEL_Z_ON ,.ch2_z_DEM_MSB_OUT0 ( ch2_z_DEM_MSB_OUT0 ) ,.ch2_z_DEM_MSB_OUT1 ( ch2_z_DEM_MSB_OUT1 ) ,.ch2_z_DEM_MSB_OUT2 ( ch2_z_DEM_MSB_OUT2 ) ,.ch2_z_DEM_MSB_OUT3 ( ch2_z_DEM_MSB_OUT3 ) ,.ch2_z_DEM_ISB_OUT0 ( ch2_z_DEM_ISB_OUT0 ) ,.ch2_z_DEM_ISB_OUT1 ( ch2_z_DEM_ISB_OUT1 ) ,.ch2_z_DEM_ISB_OUT2 ( ch2_z_DEM_ISB_OUT2 ) ,.ch2_z_DEM_ISB_OUT3 ( ch2_z_DEM_ISB_OUT3 ) ,.ch2_z_DEM_LSB_OUT0 ( ch2_z_DEM_LSB_OUT0 ) ,.ch2_z_DEM_LSB_OUT1 ( ch2_z_DEM_LSB_OUT1 ) ,.ch2_z_DEM_LSB_OUT2 ( ch2_z_DEM_LSB_OUT2 ) ,.ch2_z_DEM_LSB_OUT3 ( ch2_z_DEM_LSB_OUT3 ) `endif //------------------------------Ch3 DSP data out---------------------------------------------------- `ifdef CHANNEL_XY_ON ,.ch3_xy_A_DEM_MSB_OUT0 ( ch3_xy_A_DEM_MSB_OUT0 ) ,.ch3_xy_A_DEM_MSB_OUT1 ( ch3_xy_A_DEM_MSB_OUT1 ) ,.ch3_xy_A_DEM_MSB_OUT2 ( ch3_xy_A_DEM_MSB_OUT2 ) ,.ch3_xy_A_DEM_MSB_OUT3 ( ch3_xy_A_DEM_MSB_OUT3 ) ,.ch3_xy_A_DEM_MSB_OUT4 ( ch3_xy_A_DEM_MSB_OUT4 ) ,.ch3_xy_A_DEM_MSB_OUT5 ( ch3_xy_A_DEM_MSB_OUT5 ) ,.ch3_xy_A_DEM_MSB_OUT6 ( ch3_xy_A_DEM_MSB_OUT6 ) ,.ch3_xy_A_DEM_MSB_OUT7 ( ch3_xy_A_DEM_MSB_OUT7 ) ,.ch3_xy_B_DEM_MSB_OUT0 ( ch3_xy_B_DEM_MSB_OUT0 ) ,.ch3_xy_B_DEM_MSB_OUT1 ( ch3_xy_B_DEM_MSB_OUT1 ) ,.ch3_xy_B_DEM_MSB_OUT2 ( ch3_xy_B_DEM_MSB_OUT2 ) ,.ch3_xy_B_DEM_MSB_OUT3 ( ch3_xy_B_DEM_MSB_OUT3 ) ,.ch3_xy_B_DEM_MSB_OUT4 ( ch3_xy_B_DEM_MSB_OUT4 ) ,.ch3_xy_B_DEM_MSB_OUT5 ( ch3_xy_B_DEM_MSB_OUT5 ) ,.ch3_xy_B_DEM_MSB_OUT6 ( ch3_xy_B_DEM_MSB_OUT6 ) ,.ch3_xy_B_DEM_MSB_OUT7 ( ch3_xy_B_DEM_MSB_OUT7 ) ,.ch3_xy_A_DEM_ISB_OUT0 ( ch3_xy_A_DEM_ISB_OUT0 ) ,.ch3_xy_A_DEM_ISB_OUT1 ( ch3_xy_A_DEM_ISB_OUT1 ) ,.ch3_xy_A_DEM_ISB_OUT2 ( ch3_xy_A_DEM_ISB_OUT2 ) ,.ch3_xy_A_DEM_ISB_OUT3 ( ch3_xy_A_DEM_ISB_OUT3 ) ,.ch3_xy_A_DEM_ISB_OUT4 ( ch3_xy_A_DEM_ISB_OUT4 ) ,.ch3_xy_A_DEM_ISB_OUT5 ( ch3_xy_A_DEM_ISB_OUT5 ) ,.ch3_xy_A_DEM_ISB_OUT6 ( ch3_xy_A_DEM_ISB_OUT6 ) ,.ch3_xy_A_DEM_ISB_OUT7 ( ch3_xy_A_DEM_ISB_OUT7 ) ,.ch3_xy_B_DEM_ISB_OUT0 ( ch3_xy_B_DEM_ISB_OUT0 ) ,.ch3_xy_B_DEM_ISB_OUT1 ( ch3_xy_B_DEM_ISB_OUT1 ) ,.ch3_xy_B_DEM_ISB_OUT2 ( ch3_xy_B_DEM_ISB_OUT2 ) ,.ch3_xy_B_DEM_ISB_OUT3 ( ch3_xy_B_DEM_ISB_OUT3 ) ,.ch3_xy_B_DEM_ISB_OUT4 ( ch3_xy_B_DEM_ISB_OUT4 ) ,.ch3_xy_B_DEM_ISB_OUT5 ( ch3_xy_B_DEM_ISB_OUT5 ) ,.ch3_xy_B_DEM_ISB_OUT6 ( ch3_xy_B_DEM_ISB_OUT6 ) ,.ch3_xy_B_DEM_ISB_OUT7 ( ch3_xy_B_DEM_ISB_OUT7 ) ,.ch3_xy_A_DEM_LSB_OUT0 ( ch3_xy_A_DEM_LSB_OUT0 ) ,.ch3_xy_A_DEM_LSB_OUT1 ( ch3_xy_A_DEM_LSB_OUT1 ) ,.ch3_xy_A_DEM_LSB_OUT2 ( ch3_xy_A_DEM_LSB_OUT2 ) ,.ch3_xy_A_DEM_LSB_OUT3 ( ch3_xy_A_DEM_LSB_OUT3 ) ,.ch3_xy_A_DEM_LSB_OUT4 ( ch3_xy_A_DEM_LSB_OUT4 ) ,.ch3_xy_A_DEM_LSB_OUT5 ( ch3_xy_A_DEM_LSB_OUT5 ) ,.ch3_xy_A_DEM_LSB_OUT6 ( ch3_xy_A_DEM_LSB_OUT6 ) ,.ch3_xy_A_DEM_LSB_OUT7 ( ch3_xy_A_DEM_LSB_OUT7 ) ,.ch3_xy_B_DEM_LSB_OUT0 ( ch3_xy_B_DEM_LSB_OUT0 ) ,.ch3_xy_B_DEM_LSB_OUT1 ( ch3_xy_B_DEM_LSB_OUT1 ) ,.ch3_xy_B_DEM_LSB_OUT2 ( ch3_xy_B_DEM_LSB_OUT2 ) ,.ch3_xy_B_DEM_LSB_OUT3 ( ch3_xy_B_DEM_LSB_OUT3 ) ,.ch3_xy_B_DEM_LSB_OUT4 ( ch3_xy_B_DEM_LSB_OUT4 ) ,.ch3_xy_B_DEM_LSB_OUT5 ( ch3_xy_B_DEM_LSB_OUT5 ) ,.ch3_xy_B_DEM_LSB_OUT6 ( ch3_xy_B_DEM_LSB_OUT6 ) ,.ch3_xy_B_DEM_LSB_OUT7 ( ch3_xy_B_DEM_LSB_OUT7 ) `endif `ifdef CHANNEL_Z_ON ,.ch3_z_DEM_MSB_OUT0 ( ch3_z_DEM_MSB_OUT0 ) ,.ch3_z_DEM_MSB_OUT1 ( ch3_z_DEM_MSB_OUT1 ) ,.ch3_z_DEM_MSB_OUT2 ( ch3_z_DEM_MSB_OUT2 ) ,.ch3_z_DEM_MSB_OUT3 ( ch3_z_DEM_MSB_OUT3 ) ,.ch3_z_DEM_ISB_OUT0 ( ch3_z_DEM_ISB_OUT0 ) ,.ch3_z_DEM_ISB_OUT1 ( ch3_z_DEM_ISB_OUT1 ) ,.ch3_z_DEM_ISB_OUT2 ( ch3_z_DEM_ISB_OUT2 ) ,.ch3_z_DEM_ISB_OUT3 ( ch3_z_DEM_ISB_OUT3 ) ,.ch3_z_DEM_LSB_OUT0 ( ch3_z_DEM_LSB_OUT0 ) ,.ch3_z_DEM_LSB_OUT1 ( ch3_z_DEM_LSB_OUT1 ) ,.ch3_z_DEM_LSB_OUT2 ( ch3_z_DEM_LSB_OUT2 ) ,.ch3_z_DEM_LSB_OUT3 ( ch3_z_DEM_LSB_OUT3 ) `endif `endif ); assign pll_if.ref_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_sel ; assign pll_if.ref_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_en ; assign pll_if.ref_s2d_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.ref_s2d_en ; assign pll_if.p_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.p_cnt ; assign pll_if.pfd_delay = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_delay ; assign pll_if.pfd_dff_Set = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_dff_Set ; assign pll_if.pfd_dff_4and = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_dff_4and ; assign pll_if.spd_div = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_div ; assign pll_if.spd_pulse_width = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_pulse_width; assign pll_if.spd_pulse_sw = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_pulse_sw ; assign pll_if.cpc_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.cpc_sel ; assign pll_if.swcp_i = U_xyz_chip_top.U_digital_top.U_intpll_regfile.swcp_i ; assign pll_if.sw_ptat_r = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_ptat_r ; assign pll_if.sw_fll_cpi = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_fll_cpi ; assign pll_if.sw_fll_delay = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sw_fll_delay ; assign pll_if.pfd_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pfd_sel ; assign pll_if.spd_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.spd_sel ; assign pll_if.fll_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.fll_sel ; assign pll_if.vco_tc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_tc ; assign pll_if.vco_tcr = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_tcr ; assign pll_if.vco_gain_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_gain_adj ; assign pll_if.vco_gain_adj_r = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_gain_adj_r ; assign pll_if.vco_cur_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_cur_adj ; assign pll_if.vco_buff_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_buff_en ; assign pll_if.vco_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_en ; assign pll_if.pll_dpwr_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pll_dpwr_adj ; assign pll_if.vco_fb_adj = U_xyz_chip_top.U_digital_top.U_intpll_regfile.vco_fb_adj ; assign pll_if.afc_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_en ; assign pll_if.afc_shutdown = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_shutdown ; assign pll_if.afc_det_speed = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_det_speed ; assign pll_if.flag_out_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.flag_out_sel ; assign pll_if.afc_reset = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_reset ; assign pll_if.afc_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_cnt ; assign pll_if.afc_ld_cnt = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_ld_cnt ; assign pll_if.afc_pres = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_pres ; assign pll_if.afc_ld_tcc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_ld_tcc ; assign pll_if.afc_fb_tcc = U_xyz_chip_top.U_digital_top.U_intpll_regfile.afc_fb_tcc ; assign pll_if.div_rstn_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.div_rstn_sel ; assign pll_if.test_clk_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.test_clk_sel ; assign pll_if.test_clk_oen = U_xyz_chip_top.U_digital_top.U_intpll_regfile.test_clk_oen ; assign pll_if.dig_clk_sel = U_xyz_chip_top.U_digital_top.U_intpll_regfile.dig_clk_sel ; assign pll_if.div_sync_en = U_xyz_chip_top.U_digital_top.U_intpll_regfile.div_sync_en ; assign pll_if.sync_oe = U_xyz_chip_top.U_digital_top.U_intpll_regfile.sync_oe ; assign pll_if.pll_lock = U_xyz_chip_top.U_digital_top.U_intpll_regfile.pll_lock ; assign dac_if.Prbs = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs ; assign dac_if.Set0 = U_xyz_chip_top.U_digital_top.ch0_dac_Set0 ; assign dac_if.Set1 = U_xyz_chip_top.U_digital_top.ch0_dac_Set1 ; assign dac_if.Set2 = U_xyz_chip_top.U_digital_top.ch0_dac_Set2 ; assign dac_if.Set3 = U_xyz_chip_top.U_digital_top.ch0_dac_Set3 ; assign dac_if.Set4 = U_xyz_chip_top.U_digital_top.ch0_dac_Set4 ; assign dac_if.Set5 = U_xyz_chip_top.U_digital_top.ch0_dac_Set5 ; assign dac_if.Set6 = U_xyz_chip_top.U_digital_top.ch0_dac_Set6 ; assign dac_if.Set7 = U_xyz_chip_top.U_digital_top.ch0_dac_Set7 ; assign dac_if.Set8 = U_xyz_chip_top.U_digital_top.ch0_dac_Set8 ; assign dac_if.Set9 = U_xyz_chip_top.U_digital_top.ch0_dac_Set9 ; assign dac_if.Set10 = U_xyz_chip_top.U_digital_top.ch0_dac_Set10 ; assign dac_if.Set11 = U_xyz_chip_top.U_digital_top.ch0_dac_Set11 ; assign dac_if.Set12 = U_xyz_chip_top.U_digital_top.ch0_dac_Set12 ; assign dac_if.Set13 = U_xyz_chip_top.U_digital_top.ch0_dac_Set13 ; assign dac_if.Set14 = U_xyz_chip_top.U_digital_top.ch0_dac_Set14 ; assign dac_if.Set15 = U_xyz_chip_top.U_digital_top.ch0_dac_Set15 ; assign dac_if.Dac_addr = U_xyz_chip_top.U_digital_top.ch0_dac_addr ; assign dac_if.Dac_dw = U_xyz_chip_top.U_digital_top.ch0_dac_dw ; assign dac_if.Dac_ref = U_xyz_chip_top.U_digital_top.ch0_dac_ref ; assign dac_if.Prbs_rst0 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_rst0 ; assign dac_if.Prbs_set0 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_set0 ; assign dac_if.Prbs_rst1 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_rst1 ; assign dac_if.Prbs_set1 = U_xyz_chip_top.U_digital_top.ch0_dac_Prbs_set1 ; assign dac_if.Cal_sig = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_sig ; assign dac_if.Cal_rstn = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_rstn ; assign dac_if.Cal_div_rstn = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_div_rstn; assign dac_if.Cal_end = U_xyz_chip_top.U_digital_top.ch0_dac_Cal_end ; assign sys_if.dbg_enable = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_enable ; assign sys_if.dbg_data_sel = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_data_sel ; assign sys_if.dbg_ch_sel = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_ch_sel ; assign sys_if.status[28] = U_xyz_chip_top.U_digital_top.U_system_regfile.dbg_upd ; assign sys_if.status[ 3] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_proc_cft ; assign sys_if.status[ 2] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_ldst_addr_unalgn; assign sys_if.status[ 1] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_dec_err ; assign sys_if.status[ 0] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_exit_irq ; assign sys_if.status[11] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_proc_cft ; assign sys_if.status[10] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_ldst_addr_unalgn; assign sys_if.status[ 9] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_dec_err ; assign sys_if.status[ 8] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_exit_irq ; assign sys_if.status[19] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_proc_cft ; assign sys_if.status[18] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_ldst_addr_unalgn; assign sys_if.status[17] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_dec_err ; assign sys_if.status[16] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_exit_irq ; assign sys_if.status[27] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_proc_cft ; assign sys_if.status[26] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_ldst_addr_unalgn; assign sys_if.status[25] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_dec_err ; assign sys_if.status[24] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_exit_irq ; assign sys_if.soft_rstn[0] = U_xyz_chip_top.U_digital_top.U_system_regfile.sys_soft_rstn ; assign sys_if.soft_rstn[1] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch0_soft_rstn ; assign sys_if.soft_rstn[2] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch1_soft_rstn ; assign sys_if.soft_rstn[3] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch2_soft_rstn ; assign sys_if.soft_rstn[4] = U_xyz_chip_top.U_digital_top.U_system_regfile.ch3_soft_rstn ; assign sys_if.irq = U_xyz_chip_top.U_digital_top.U_system_regfile.irq ; assign mcu_if.wrmask = U_xyz_chip_top.U_digital_top.U0_channel_top.U_mcu_regfile.wrmask ; assign awg_if.fb_st_i = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.fb_st_i ; assign awg_if.run_time = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.run_time ; assign awg_if.instr_num = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.instr_num ; assign awg_if.bais_i_ov = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.bais_i_ov ; assign awg_if.bais_q_ov = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.bais_q_ov ; assign awg_if.awg_ctrl_fsm_st = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.awg_ctrl_fsm_st ; assign awg_if.mcu_param0 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param0 ; assign awg_if.mcu_param1 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param1 ; assign awg_if.mcu_param2 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param2 ; assign awg_if.mcu_param3 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_param3 ; assign awg_if.mcu_result0 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result0 ; assign awg_if.mcu_result1 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result1 ; assign awg_if.mcu_result2 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result2 ; assign awg_if.mcu_result3 = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mcu_result3 ; assign awg_if.fb_st_o = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.fb_st_o ; assign awg_if.mod_sel_sideband = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.mod_sel_sideband; assign awg_if.qam_nco_clr = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_nco_clr ; assign awg_if.qam_nco_sclr_en = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_nco_sclr_en ; assign awg_if.qam_fcw = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_fcw ; assign awg_if.qam_pha = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_pha ; assign awg_if.qam_mod = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_mod ; assign awg_if.qam_sel_sideband = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.qam_sel_sideband; assign awg_if.intp_mode = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.intp_mode ; assign awg_if.role_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.role_sel ; assign awg_if.dac_mode_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.dac_mode_sel ; assign awg_if.dout_sel = U_xyz_chip_top.U_digital_top.U0_channel_top.U_ctrl_regfile.dout_sel ; wire [15 :0] ch0_mod_data_i = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_i ; wire [15 :0] ch0_mod_data_q = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_data_q ; wire ch0_mod_vld = U_xyz_chip_top.U_digital_top. U_debug_top.U_debug_sampling.ch0_mod_vld ; wire [511:0] mod_data_c = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_data_c ; wire mod_cen = U_xyz_chip_top.U_digital_top.U_debug_top.U_debug_sampling.mod_cen ; case6 test(spi_if,pll_if,dac_if,sys_if,mcu_if,awg_if,mst); int seed; initial begin $value$plusargs("ntb_random_seed=%d", seed); end endmodule