//For ram_regfile 
class ram_refmodel; 

    virtual spi_if		    wif;
    virtual sram_if#(25,32)	xif;

    int base_addr;
    int sel;
    //poor-quality register model
    bit [31:0] rm1[8192];
    bit [31:0] rm2[  64];
    bit [31:0] rm3[1024];

    //members to be sent to scoreboard
    int 			rst_error[5];
    bit[31:0]   		dout[$];
    spi_trans		ramout[$];

    function new();

    endfunction
    extern task do_imitate();
    extern task RWreg_write	    (bit[24:0] addr,bit[32:0] din);
    extern task reg_read		(bit[24:0] addr			     );

endclass : ram_refmodel

task ram_refmodel::do_imitate();
    
    int		i=0,j=0;


    fork


      while(1) begin:  write_reg_RW
	
 	    @(negedge xif.wren);

	    RWreg_write(xif.addr,xif.din);

      end:  write_reg_RW


      while(1) begin: read_reg

	    @(negedge xif.rden);
//            repeat(3) @(posedge xif.clk);

	    reg_read(xif.addr);

      end:  read_reg

    join

endtask: do_imitate

task ram_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din);
   
    @(posedge wif.clk);   
    
    if(addr[24:20] ==  base_addr) begin      
      case(sel)
        1:rm1[addr[15:2]] =  din;  
        2:rm2[addr[15:2]] =  din;  
        3:rm3[addr[15:2]] =  din;  
      endcase
    end
//$display("addr:%0h",addr);
//$display("rm[%d]:%h",addr[15:2],rm2[addr[15:2]]);
//$display("din:%h",din);


endtask:  RWreg_write

task ram_refmodel::reg_read(bit[24:0] addr);
    
    @(posedge wif.clk);

    if(addr[24:20] ==  base_addr) begin
       case(sel)
         1:dout.push_back(rm1[ addr[14:2]]);  
         2:dout.push_back(rm2[ addr[14:2]]);  
         3:dout.push_back(rm3[ addr[14:2]]);  
       endcase
      
    end
//       $display("dout:%h",dout[$]);
endtask:  reg_read