wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
reg ram_cs_dly1 ;
reg reg_en_dly1 ;
always @(posedge ram_clk) begin
    ram_cs_dly1 <= ~ram_cs;
    reg_en_dly1 <= reg_en;
end


initial begin
    #1ns;
    //@(posedge ram_cs_dly1 );
    #5ns;
    //while(1)begin
        #1ns;
    //@(posedge reg_en_dly1 );
            REGFILE_CHECK(6'd1 ,32'h5555_5000);
			REGFILE_CHECK(6'd1 ,32'h5555_5004);
			REGFILE_CHECK(6'd1 ,32'h5555_5008);
			REGFILE_CHECK(6'd1 ,32'h5555_500c);
            REGFILE_CHECK(6'd2 ,32'h5555_5010);
			REGFILE_CHECK(6'd2 ,32'h5555_5014);
			REGFILE_CHECK(6'd2 ,32'h5555_5018);
			REGFILE_CHECK(6'd2 ,32'h5555_501c);
			REGFILE_CHECK(6'd3 ,32'h5555_5020);
			REGFILE_CHECK(6'd3 ,32'h5555_5024);
			REGFILE_CHECK(6'd3 ,32'h5555_5028);
			REGFILE_CHECK(6'd3 ,32'h5555_502c);
			REGFILE_CHECK(6'd4 ,32'h5555_5030);
			REGFILE_CHECK(6'd4 ,32'h5555_5034);
			REGFILE_CHECK(6'd4 ,32'h5555_5038);
			REGFILE_CHECK(6'd4 ,32'h5555_503c);
			REGFILE_CHECK(6'd5 ,32'h5555_5040);
			REGFILE_CHECK(6'd5 ,32'h5555_5044);
			REGFILE_CHECK(6'd5 ,32'h5555_5048);
			REGFILE_CHECK(6'd5 ,32'h5555_504c);
			REGFILE_CHECK(6'd6 ,32'h5555_5050);
			REGFILE_CHECK(6'd6 ,32'h5555_5054);
			REGFILE_CHECK(6'd6 ,32'h5555_5058);
			REGFILE_CHECK(6'd6 ,32'h5555_505c);
			REGFILE_CHECK(6'd7 ,32'h5555_5060);
			REGFILE_CHECK(6'd7 ,32'h5555_5064);
			REGFILE_CHECK(6'd7 ,32'h5555_5068);
			REGFILE_CHECK(6'd7 ,32'h5555_506c);
			REGFILE_CHECK(6'd8 ,32'h5555_5070);
			REGFILE_CHECK(6'd8 ,32'h5555_5074);
			REGFILE_CHECK(6'd8 ,32'h5555_5078);
			REGFILE_CHECK(6'd8 ,32'h5555_507c);
			REGFILE_CHECK(6'd9 ,32'h5555_5080);
			REGFILE_CHECK(6'd9 ,32'h5555_5084);
			REGFILE_CHECK(6'd9 ,32'h5555_5088);
			REGFILE_CHECK(6'd9 ,32'h5555_508c);
			REGFILE_CHECK(6'd10,32'h5555_5090);
			REGFILE_CHECK(6'd10,32'h5555_5094);
			REGFILE_CHECK(6'd10,32'h5555_5098);
			REGFILE_CHECK(6'd10,32'h5555_509c);
			REGFILE_CHECK(6'd11,32'h5555_50a0);
			REGFILE_CHECK(6'd11,32'h5555_50a4);
			REGFILE_CHECK(6'd11,32'h5555_50a8);
			REGFILE_CHECK(6'd11,32'h5555_50ac);
			REGFILE_CHECK(6'd12,32'h5555_50b0);
			REGFILE_CHECK(6'd12,32'h5555_50b4);
			REGFILE_CHECK(6'd12,32'h5555_50b8);
			REGFILE_CHECK(6'd12,32'h5555_50bc);
			REGFILE_CHECK(6'd13,32'h5555_50c0);
			REGFILE_CHECK(6'd13,32'h5555_50c4);
			REGFILE_CHECK(6'd13,32'h5555_50c8);
			REGFILE_CHECK(6'd13,32'h5555_50cc);
			REGFILE_CHECK(6'd14,32'h5555_50d0);
			REGFILE_CHECK(6'd14,32'h5555_50d4);
			REGFILE_CHECK(6'd14,32'h5555_50d8);
			REGFILE_CHECK(6'd14,32'h5555_50dc);
			REGFILE_CHECK(6'd15,32'h5555_50e0);
			REGFILE_CHECK(6'd15,32'h5555_50e4);
			REGFILE_CHECK(6'd15,32'h5555_50e8);
			REGFILE_CHECK(6'd15,32'h5555_50ec);
			REGFILE_CHECK(6'd16,32'h5555_50f0);
			REGFILE_CHECK(6'd16,32'h5555_50f4);
			REGFILE_CHECK(6'd16,32'h5555_50f8);
			REGFILE_CHECK(6'd16,32'h5555_50fc);
			REGFILE_CHECK(6'd17,32'h5555_5100);
			REGFILE_CHECK(6'd17,32'h5555_5104);
			REGFILE_CHECK(6'd17,32'h5555_5108);
			REGFILE_CHECK(6'd17,32'h5555_510c);
			REGFILE_CHECK(6'd18,32'h5555_5110);
			REGFILE_CHECK(6'd18,32'h5555_5114);
			REGFILE_CHECK(6'd18,32'h5555_5118);
			REGFILE_CHECK(6'd18,32'h5555_511c);
			REGFILE_CHECK(6'd19,32'h5555_5120);
			REGFILE_CHECK(6'd19,32'h5555_5124);
			REGFILE_CHECK(6'd19,32'h5555_5128);
			REGFILE_CHECK(6'd19,32'h5555_512c);
			REGFILE_CHECK(6'd20,32'h5555_5130);
			REGFILE_CHECK(6'd20,32'h5555_5134);
			REGFILE_CHECK(6'd20,32'h5555_5138);
			REGFILE_CHECK(6'd20,32'h5555_513c);
			REGFILE_CHECK(6'd21,32'h5555_5140);
			REGFILE_CHECK(6'd21,32'h5555_5144);
			REGFILE_CHECK(6'd21,32'h5555_5148);
			REGFILE_CHECK(6'd21,32'h5555_514c);
			REGFILE_CHECK(6'd22,32'h5555_5150);
			REGFILE_CHECK(6'd22,32'h5555_5154);
			REGFILE_CHECK(6'd22,32'h5555_5158);
			REGFILE_CHECK(6'd22,32'h5555_515c);
			REGFILE_CHECK(6'd23,32'h5555_5160);
			REGFILE_CHECK(6'd23,32'h5555_5164);
			REGFILE_CHECK(6'd23,32'h5555_5168);
			REGFILE_CHECK(6'd23,32'h5555_516c);
			REGFILE_CHECK(6'd24,32'h5555_5170);
			REGFILE_CHECK(6'd24,32'h5555_5174);
			REGFILE_CHECK(6'd24,32'h5555_5178);
			REGFILE_CHECK(6'd24,32'h5555_517c);
			REGFILE_CHECK(6'd25,32'h5555_5180);
			REGFILE_CHECK(6'd25,32'h5555_5184);
			REGFILE_CHECK(6'd25,32'h5555_5188);
			REGFILE_CHECK(6'd25,32'h5555_518c);
			REGFILE_CHECK(6'd26,32'h5555_5190);
			REGFILE_CHECK(6'd26,32'h5555_5194);
			REGFILE_CHECK(6'd26,32'h5555_5198);
			REGFILE_CHECK(6'd26,32'h5555_519c);
			REGFILE_CHECK(6'd27,32'h5555_51a0);
			REGFILE_CHECK(6'd27,32'h5555_51a4);
			REGFILE_CHECK(6'd27,32'h5555_51a8);
			REGFILE_CHECK(6'd27,32'h5555_51ac);
			REGFILE_CHECK(6'd28,32'h5555_51b0);
			REGFILE_CHECK(6'd28,32'h5555_51b4);
			REGFILE_CHECK(6'd28,32'h5555_51b8);
			REGFILE_CHECK(6'd28,32'h5555_51bc);
			REGFILE_CHECK(6'd29,32'h5555_51c0);
			REGFILE_CHECK(6'd29,32'h5555_51c4);
			REGFILE_CHECK(6'd29,32'h5555_51c8);
			REGFILE_CHECK(6'd29,32'h5555_51cc);
			REGFILE_CHECK(6'd30,32'h5555_51d0);
			REGFILE_CHECK(6'd30,32'h5555_51d4);
			REGFILE_CHECK(6'd30,32'h5555_51d8);
			REGFILE_CHECK(6'd30,32'h5555_51dc);
			REGFILE_CHECK(6'd31,32'h5555_51e0);
			REGFILE_CHECK(6'd31,32'h5555_51e4);
			REGFILE_CHECK(6'd31,32'h5555_51e8);
			REGFILE_CHECK(6'd31,32'h5555_51ec);
    #10us;
    TEST_PASS;
end

task DRAM_DATA_CHECK;
    input   [9:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  ram_data;

    @(posedge ram_cs_dly1 );
    @(posedge ram_clk );
     //$monitor($time, " Simulation time: %t", $time);
    if(ram_cs_dly1) begin
        ram_data = `TB_DRAM.mem[addr];
        //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
        if(ram_data !== edata) begin
            $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
            #1us;
            TEST_FAIL;
        end
        $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
    end
    else begin
            $display("* DRAM CS is High => Error!!!");
            TEST_FAIL;
    end
endtask

task REGFILE_CHECK;
    input   [4:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  reg_data;
    @(posedge reg_en );
    @(posedge reg_clk);
    if(reg_en)begin
        reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
        if(reg_data !== edata) begin
            $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
            #1us;
            //TEST_FAIL;
        end
        $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
    end
    else begin
            $display("* REG WR EN is High => Error!!!");
            //TEST_FAIL;
    end

endtask

initial begin
    #100us;
    $display("\n----------------------------------------\n");
    $display("\t Timeout Error !!!!\n");
    TEST_FAIL;
end