wire ram_clk = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CLK;
wire ram_cs = `TB.U_CHIP_TOP.U_DTCM.U_tsmc_dpram.dpram_32X4096_generation.U0_TSDN28HPCPUHDB4096X32M4MWR.CEBA;
wire reg_clk = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.clk;
wire reg_en = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_wen;
reg ram_cs_dly1 ;
reg reg_en_dly1 ;
always @(posedge ram_clk) begin
    ram_cs_dly1 <= ~ram_cs;
    reg_en_dly1 <= reg_en;
end


initial begin
    #1ns;
    //@(posedge ram_cs_dly1 );
    #5ns;
    //while(1)begin
        #1ns;
    //@(posedge reg_en_dly1 );
            REGFILE_CHECK(6'd1 ,32'h0000_0000);
			REGFILE_CHECK(6'd1 ,32'h0000_0004);
			REGFILE_CHECK(6'd1 ,32'h0000_0008);
			REGFILE_CHECK(6'd1 ,32'h0000_000c);
            REGFILE_CHECK(6'd2 ,32'h0000_0010);
			REGFILE_CHECK(6'd2 ,32'h0000_0014);
			REGFILE_CHECK(6'd2 ,32'h0000_0018);
			REGFILE_CHECK(6'd2 ,32'h0000_001c);
			REGFILE_CHECK(6'd3 ,32'h0000_0020);
			REGFILE_CHECK(6'd3 ,32'h0000_0024);
			REGFILE_CHECK(6'd3 ,32'h0000_0028);
			REGFILE_CHECK(6'd3 ,32'h0000_002c);
			REGFILE_CHECK(6'd4 ,32'h0000_0030);
			REGFILE_CHECK(6'd4 ,32'h0000_0034);
			REGFILE_CHECK(6'd4 ,32'h0000_0038);
			REGFILE_CHECK(6'd4 ,32'h0000_003c);
			REGFILE_CHECK(6'd5 ,32'h0000_0040);
			REGFILE_CHECK(6'd5 ,32'h0000_0044);
			REGFILE_CHECK(6'd5 ,32'h0000_0048);
			REGFILE_CHECK(6'd5 ,32'h0000_004c);
			REGFILE_CHECK(6'd6 ,32'h0000_0050);
			REGFILE_CHECK(6'd6 ,32'h0000_0054);
			REGFILE_CHECK(6'd6 ,32'h0000_0058);
			REGFILE_CHECK(6'd6 ,32'h0000_005c);
			REGFILE_CHECK(6'd7 ,32'h0000_0060);
			REGFILE_CHECK(6'd7 ,32'h0000_0064);
			REGFILE_CHECK(6'd7 ,32'h0000_0068);
			REGFILE_CHECK(6'd7 ,32'h0000_006c);
			REGFILE_CHECK(6'd8 ,32'h0000_0070);
			REGFILE_CHECK(6'd8 ,32'h0000_0074);
			REGFILE_CHECK(6'd8 ,32'h0000_0078);
			REGFILE_CHECK(6'd8 ,32'h0000_007c);
			REGFILE_CHECK(6'd9 ,32'h0000_0080);
			REGFILE_CHECK(6'd9 ,32'h0000_0084);
			REGFILE_CHECK(6'd9 ,32'h0000_0088);
			REGFILE_CHECK(6'd9 ,32'h0000_008c);
			REGFILE_CHECK(6'd10,32'h0000_0090);
			REGFILE_CHECK(6'd10,32'h0000_0094);
			REGFILE_CHECK(6'd10,32'h0000_0098);
			REGFILE_CHECK(6'd10,32'h0000_009c);
			REGFILE_CHECK(6'd11,32'h0000_00a0);
			REGFILE_CHECK(6'd11,32'h0000_00a4);
			REGFILE_CHECK(6'd11,32'h0000_00a8);
			REGFILE_CHECK(6'd11,32'h0000_00ac);
			REGFILE_CHECK(6'd12,32'h0000_00b0);
			REGFILE_CHECK(6'd12,32'h0000_00b4);
			REGFILE_CHECK(6'd12,32'h0000_00b8);
			REGFILE_CHECK(6'd12,32'h0000_00bc);
			REGFILE_CHECK(6'd13,32'h0000_00c0);
			REGFILE_CHECK(6'd13,32'h0000_00c4);
			REGFILE_CHECK(6'd13,32'h0000_00c8);
			REGFILE_CHECK(6'd13,32'h0000_00cc);
			REGFILE_CHECK(6'd14,32'h0000_00d0);
			REGFILE_CHECK(6'd14,32'h0000_00d4);
			REGFILE_CHECK(6'd14,32'h0000_00d8);
			REGFILE_CHECK(6'd14,32'h0000_00dc);
			REGFILE_CHECK(6'd15,32'h0000_00e0);
			REGFILE_CHECK(6'd15,32'h0000_00e4);
			REGFILE_CHECK(6'd15,32'h0000_00e8);
			REGFILE_CHECK(6'd15,32'h0000_00ec);
			REGFILE_CHECK(6'd16,32'h0000_00f0);
			REGFILE_CHECK(6'd16,32'h0000_00f4);
			REGFILE_CHECK(6'd16,32'h0000_00f8);
			REGFILE_CHECK(6'd16,32'h0000_00fc);
			REGFILE_CHECK(6'd17,32'h0000_0100);
			REGFILE_CHECK(6'd17,32'h0000_0104);
			REGFILE_CHECK(6'd17,32'h0000_0108);
			REGFILE_CHECK(6'd17,32'h0000_010c);
			REGFILE_CHECK(6'd18,32'h0000_0110);
			REGFILE_CHECK(6'd18,32'h0000_0114);
			REGFILE_CHECK(6'd18,32'h0000_0118);
			REGFILE_CHECK(6'd18,32'h0000_011c);
			REGFILE_CHECK(6'd19,32'h0000_0120);
			REGFILE_CHECK(6'd19,32'h0000_0124);
			REGFILE_CHECK(6'd19,32'h0000_0128);
			REGFILE_CHECK(6'd19,32'h0000_012c);
			REGFILE_CHECK(6'd20,32'h0000_0130);
			REGFILE_CHECK(6'd20,32'h0000_0134);
			REGFILE_CHECK(6'd20,32'h0000_0138);
			REGFILE_CHECK(6'd20,32'h0000_013c);
			REGFILE_CHECK(6'd21,32'h0000_0140);
			REGFILE_CHECK(6'd21,32'h0000_0144);
			REGFILE_CHECK(6'd21,32'h0000_0148);
			REGFILE_CHECK(6'd21,32'h0000_014c);
			REGFILE_CHECK(6'd22,32'h0000_0150);
			REGFILE_CHECK(6'd22,32'h0000_0154);
			REGFILE_CHECK(6'd22,32'h0000_0158);
			REGFILE_CHECK(6'd22,32'h0000_015c);
			REGFILE_CHECK(6'd23,32'h0000_0160);
			REGFILE_CHECK(6'd23,32'h0000_0164);
			REGFILE_CHECK(6'd23,32'h0000_0168);
			REGFILE_CHECK(6'd23,32'h0000_016c);
			REGFILE_CHECK(6'd24,32'h0000_0170);
			REGFILE_CHECK(6'd24,32'h0000_0174);
			REGFILE_CHECK(6'd24,32'h0000_0178);
			REGFILE_CHECK(6'd24,32'h0000_017c);
			REGFILE_CHECK(6'd25,32'h0000_0180);
			REGFILE_CHECK(6'd25,32'h0000_0184);
			REGFILE_CHECK(6'd25,32'h0000_0188);
			REGFILE_CHECK(6'd25,32'h0000_018c);
			REGFILE_CHECK(6'd26,32'h0000_0190);
			REGFILE_CHECK(6'd26,32'h0000_0194);
			REGFILE_CHECK(6'd26,32'h0000_0198);
			REGFILE_CHECK(6'd26,32'h0000_019c);
			REGFILE_CHECK(6'd27,32'h0000_01a0);
			REGFILE_CHECK(6'd27,32'h0000_01a4);
			REGFILE_CHECK(6'd27,32'h0000_01a8);
			REGFILE_CHECK(6'd27,32'h0000_01ac);
			REGFILE_CHECK(6'd28,32'h0000_01b0);
			REGFILE_CHECK(6'd28,32'h0000_01b4);
			REGFILE_CHECK(6'd28,32'h0000_01b8);
			REGFILE_CHECK(6'd28,32'h0000_01bc);
			REGFILE_CHECK(6'd29,32'h0000_01c0);
			REGFILE_CHECK(6'd29,32'h0000_01c4);
			REGFILE_CHECK(6'd29,32'h0000_01c8);
			REGFILE_CHECK(6'd29,32'h0000_01cc);
			REGFILE_CHECK(6'd30,32'h0000_01d0);
			REGFILE_CHECK(6'd30,32'h0000_01d4);
			REGFILE_CHECK(6'd30,32'h0000_01d8);
			REGFILE_CHECK(6'd30,32'h0000_01dc);
			REGFILE_CHECK(6'd31,32'h0000_01e0);
			REGFILE_CHECK(6'd31,32'h0000_01e4);
			REGFILE_CHECK(6'd31,32'h0000_01e8);
			REGFILE_CHECK(6'd31,32'h0000_01ec);
    #10us;
    TEST_PASS;
end

task DRAM_DATA_CHECK;
    input   [9:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  ram_data;

    @(posedge ram_cs_dly1 );
    @(posedge ram_clk );
     //$monitor($time, " Simulation time: %t", $time);
    if(ram_cs_dly1) begin
        ram_data = `TB_DRAM.mem[addr];
        //$display("* RAM_DATA[%x]: %x | EXP_DATA: %x ",addr,ram_data, edata);
        if(ram_data !== edata) begin
            $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,ram_data, edata);
            #1us;
            TEST_FAIL;
        end
        $display("* RAM_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, ram_data, edata);
    end
    else begin
            $display("* DRAM CS is High => Error!!!");
            TEST_FAIL;
    end
endtask

task REGFILE_CHECK;
    input   [4:0]   addr    ;
    input   [31:0]  edata   ;

    logic   [31:0]  reg_data;
    @(posedge reg_en );
    @(posedge reg_clk);
    if(reg_en)begin
        reg_data = tbtop.U_CHIP_TOP.U_qbmcu.U_qbmcu_regfile.wbck_dest_dat;
        if(reg_data !== edata) begin
            $display("* REG_DATA[%x]: %x | EXP_DATA: %x => Error!!!",addr,reg_data, edata);
            #1us;
            //TEST_FAIL;
        end
        $display("* REG_DATA[%x]: %x | EXP_DATA: %x => OK!!!",addr, reg_data, edata);
    end
    else begin
            $display("* REG WR EN is High => Error!!!");
            //TEST_FAIL;
    end

endtask

initial begin
    #100us;
    $display("\n----------------------------------------\n");
    $display("\t Timeout Error !!!!\n");
    TEST_FAIL;
end