interface dacreg_if(input clk,input rstn); 
//input port  
   logic         Cal_end     ;
//output port
   logic         Prbs        ; 
   logic [14 :0] Set0        ;
   logic [14 :0] Set1        ;
   logic [14 :0] Set2        ;
   logic [14 :0] Set3        ;
   logic [14 :0] Set4        ;
   logic [14 :0] Set5        ;
   logic [14 :0] Set6        ;
   logic [14 :0] Set7        ;
   logic [14 :0] Set8        ;
   logic [14 :0] Set9        ;
   logic [14 :0] Set10       ;
   logic [14 :0] Set11       ;
   logic [14 :0] Set12       ;
   logic [14 :0] Set13       ;
   logic [14 :0] Set14       ;
   logic [14 :0] Set15       ;
   logic [2  :0] Dac_addr    ;
   logic [2  :0] Dac_dw      ;
   logic [8  :0] Dac_ref     ;
   logic [16 :0] Prbs_rst0   ;
   logic [16 :0] Prbs_set0   ;
   logic [16 :0] Prbs_rst1   ;
   logic [16 :0] Prbs_set1   ; 
   logic         Cal_sig     ;
   logic         Cal_rstn    ;
   logic         Cal_div_rstn;

endinterface : dacreg_if