//For awg_regfile, the ROreg: mcu_resr/rtimr/icntr/fsir are updated by the inputs //at this clk_posedge due to dff(inputs->regs) class awg_refmodel; virtual awgreg_if aif; virtual spi_if wif; virtual sram_if#(25,32) xif; //poor-quality register model bit[31:0] rm[24]; //members to be sent to scoreboard int rst_error[5]; bit[31:0] dout[$]; awgreg_trans awgout[$]; function new(); endfunction extern task do_imitate(); extern task RWreg_write (bit[24:0] addr,bit[32:0] din ); extern task ROreg_update (bit[24:0] addr ); extern task reg_read (bit[24:0] addr ); extern task output_trace (bit[24:0] addr ); endclass : awg_refmodel task awg_refmodel::do_imitate(); int i=0,j=0; rm[ 0] = 32'h0; //MCUPARAR0 rm[ 1] = 32'h0; //MCUPARAR1 rm[ 2] = 32'h0; //MCUPARAR2 rm[ 3] = 32'h0; //MCUPARAR3 rm[ 4] = 32'h0; //MCURESR0 rm[ 5] = 32'h0; //MCURESR1 rm[ 6] = 32'h0; //MCURESR2 rm[ 7] = 32'h0; //MCURESR3 rm[ 8] = 32'h0; //PTIMR rm[ 9] = 32'h0; //ICNTR rm[10] = 32'h0; //FSIR rm[11] = 32'h0; //MODMR rm[12] = 32'h0; //INTPMR rm[13] = 32'h0; //MIXNCOR rm[14] = 32'h0; //MIXNFCWHR rm[15] = 32'h0; //MIXNFCWLR rm[16] = 32'h0; //MIXNPHAR rm[17] = 32'h0; //MIXMR rm[18] = 32'h0; //MIXODTR rm[19] = 32'h0; //MIXODFR rm[20] = 32'h0; //ROLER rm[21] = 32'h0; //MIXNCOSCER rm[22] = 32'h0; //MODDOTR rm[23] = 32'h0; //STR fork while(1) begin: write_reg_RW @(negedge xif.wren); RWreg_write(xif.addr,xif.din); end: write_reg_RW while(1) begin: update_reg_RO ROreg_update(xif.addr); end: update_reg_RO while(1) begin: read_reg @(negedge xif.rden); reg_read(xif.addr); end: read_reg while(1) begin: output_port @(negedge xif.wren); output_trace(xif.addr); end: output_port join endtask: do_imitate task awg_refmodel::RWreg_write(bit[24:0] addr,bit[32:0] din); //delay caused by decoder @(posedge wif.clk); case(addr[24: 2]) 23'hC0000: rm[ 0] = din; //MCUPARAR0 23'hC0001: rm[ 1] = din; //MCUPARAR1 23'hC0002: rm[ 2] = din; //MCUPARAR2 23'hC0003: rm[ 3] = din; //MCUPARAR3 23'hC0040: rm[11] = {rm[11][31: 1],din[0 : 0]}; //MODMR 23'hC0041: rm[12] = {rm[12][31: 3],din[2 : 0]}; //INTPMR 23'hC0042: rm[13] = {rm[13][31: 1],din[0 : 0]}; //MIXNCOR 23'hC0043: rm[14] = din; //MIXNFCWHR 23'hC0044: rm[15] = {rm[15][31:16],din[31:16]}; //MIXNFCWLR 23'hC0045: rm[16] = {rm[16][31:16],din[31:16]}; //MIXNPHAR 23'hC0046: rm[17] = {rm[17][31: 1],din[0 : 0]}; //MIXMR 23'hC0047: rm[18] = {rm[18][31: 2],din[1 : 0]}; //MIXODTR 23'hC0048: rm[19] = {rm[19][31: 2],din[1 : 0]}; //MIXODFR 23'hC004a: rm[20] = {rm[20][31: 2],din[1 : 0]}; //ROLER 23'hC004b: rm[21] = {rm[21][31: 1],din[0 : 0]}; //MIXNCOSCER 23'hC004c: rm[22] = {rm[22][31: 1],din[0 : 0]}; //MODDOTR endcase //$display("addr:%0h",addr); //$display("rm:%h",rm[addr[24: 2]]); //$display("din:%h",din); endtask: RWreg_write task awg_refmodel::ROreg_update(bit[24:0] addr); @(posedge wif.clk); rm[ 4] = aif.mcu_result0 ; //MCURESR0 rm[ 5] = aif.mcu_result1 ; //MCURESR1 rm[ 6] = aif.mcu_result2 ; //MCURESR2 rm[ 7] = aif.mcu_result3 ; //MCURESR3 rm[ 8] = aif.run_time ; //PTIMR rm[ 9] = aif.instr_num ; //ICNTR rm[10] = {rm[10][31:2],aif.fb_st_i[1:0]} ; //FSIR rm[23] = {rm[23][31:3],aif.bais_q_ov,aif.bais_i_ov,aif.awg_ctrl_fsm_st} ; //STR endtask: ROreg_update task awg_refmodel::reg_read(bit[24:0] addr); //delay caused be decoder //@(posedge wif.clk); case(addr[24: 2]) 23'hC0000: dout.push_back(rm[ 0]); //MCUPARAR0 23'hC0001: dout.push_back(rm[ 1]); //MCUPARAR1 23'hC0002: dout.push_back(rm[ 2]); //MCUPARAR2 23'hC0003: dout.push_back(rm[ 3]); //MCUPARAR3 23'hC0004: dout.push_back(rm[ 4]); //MCURESR0 23'hC0005: dout.push_back(rm[ 5]); //MCURESR1 23'hC0006: dout.push_back(rm[ 6]); //MCURESR2 23'hC0007: dout.push_back(rm[ 7]); //MCURESR3 23'hC0008: dout.push_back(0); 23'hC0026: dout.push_back(rm[ 8]); //PTIMR 23'hC0027: dout.push_back(rm[ 9]); //ICNTR 23'hC0028: dout.push_back(rm[10]); //FSIR 23'hC0029: dout.push_back(0); 23'hC0040: dout.push_back(rm[11]); //MODMR 23'hC0041: dout.push_back(rm[12]); //INTPMR 23'hC0042: dout.push_back(rm[13]); //MIXNCOR 23'hC0043: dout.push_back(rm[14]); //MIXNFCWHR 23'hC0044: dout.push_back(rm[15]); //MIXNFCWLR 23'hC0045: dout.push_back(rm[16]); //MIXNPHAR 23'hC0046: dout.push_back(rm[17]); //MIXMR 23'hC0047: dout.push_back(rm[18]); //MIXODTR 23'hC0048: dout.push_back(rm[19]); //MIXODFR 23'hC0049: dout.push_back(0) ; 23'hC004a: dout.push_back({rm[20][31:2],rm[20][1 : 1]&rm[20][0 :0],rm[20][0 : 0]}); //ROLER 23'hC004b: dout.push_back(rm[21]); //MIXNCOSCER 23'hC004c: dout.push_back(rm[22]); //MODDOTR 23'hC004d: dout.push_back(rm[23]); //STR 23'hC004e: dout.push_back(0); endcase //$display("addr:%0h,dout:%h",addr[24:2],dout[$]); endtask: reg_read task awg_refmodel::output_trace(bit[24:0] addr); awgreg_trans tr_temp; if(addr[24:20 == 5'h3]) begin //delay caused by decoder @(posedge wif.clk); @(negedge wif.clk); tr_temp = new(); tr_temp.mcu_param0 = rm[ 0] ; //MCUPARAR0 tr_temp.mcu_param1 = rm[ 1] ; //MCUPARAR1 tr_temp.mcu_param2 = rm[ 2] ; //MCUPARAR2 tr_temp.mcu_param3 = rm[ 3] ; //MCUPARAR3 tr_temp.fb_st_o = rm[10][1: 0] ; //FSIR tr_temp.mod_sel_sideband = rm[11][0: 0] ; //MODMR tr_temp.qam_nco_clr = rm[13][0 :0] ; //MIXNCOR tr_temp.qam_nco_sclr_en = rm[21][0 :0] ; //MIXNCOSCER tr_temp.qam_fcw = {rm[14],rm[15][15:0]} ; //MIXNFCWHR MIXNFCWLR tr_temp.qam_pha = rm[16][15: 0] ; //MIXNPHAR tr_temp.qam_mod = rm[18][1 : 0] ; //MIXODTR tr_temp.qam_sel_sideband = rm[17][0 : 0] ; //MIXMR tr_temp.intp_mode = rm[12][2 : 0] ; //INTPMR tr_temp.role_sel[0] = rm[20][0 : 0] ; //ROLER[0] tr_temp.role_sel[1] = rm[20][1 : 1]&rm[20][0 :0]; //ROLER[1] tr_temp.dac_mode_sel = rm[19][1 : 0] ; //MIXODFR tr_temp.dout_sel = rm[22][0 : 0] ; //MODDOTR awgout.push_back(tr_temp); end //$display("addr:%0h",addr); //$display("rm:%h",rm[addr[24: 2]]); //$display("din:%h",din); endtask: output_trace