//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : SSB.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.4 2024-03-12 PWY //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module SSB( input clk, input rstn, input sel_sideband, input din_vld, input mix_enable, output dout_vld, input signed [15:0] din_i0, input signed [15:0] din_i1, input signed [15:0] din_i2, input signed [15:0] din_i3, input signed [15:0] din_i4, input signed [15:0] din_i5, input signed [15:0] din_i6, input signed [15:0] din_i7, input signed [15:0] din_i8, input signed [15:0] din_i9, input signed [15:0] din_i10, input signed [15:0] din_i11, input signed [15:0] din_i12, input signed [15:0] din_i13, input signed [15:0] din_i14, input signed [15:0] din_i15, input signed [15:0] din_q0, input signed [15:0] din_q1, input signed [15:0] din_q2, input signed [15:0] din_q3, input signed [15:0] din_q4, input signed [15:0] din_q5, input signed [15:0] din_q6, input signed [15:0] din_q7, input signed [15:0] din_q8, input signed [15:0] din_q9, input signed [15:0] din_q10, input signed [15:0] din_q11, input signed [15:0] din_q12, input signed [15:0] din_q13, input signed [15:0] din_q14, input signed [15:0] din_q15, input signed [15:0] cos_0, input signed [15:0] cos_1, input signed [15:0] cos_2, input signed [15:0] cos_3, input signed [15:0] cos_4, input signed [15:0] cos_5, input signed [15:0] cos_6, input signed [15:0] cos_7, input signed [15:0] cos_8, input signed [15:0] cos_9, input signed [15:0] cos_10, input signed [15:0] cos_11, input signed [15:0] cos_12, input signed [15:0] cos_13, input signed [15:0] cos_14, input signed [15:0] cos_15, input signed [15:0] sin_0, input signed [15:0] sin_1, input signed [15:0] sin_2, input signed [15:0] sin_3, input signed [15:0] sin_4, input signed [15:0] sin_5, input signed [15:0] sin_6, input signed [15:0] sin_7, input signed [15:0] sin_8, input signed [15:0] sin_9, input signed [15:0] sin_10, input signed [15:0] sin_11, input signed [15:0] sin_12, input signed [15:0] sin_13, input signed [15:0] sin_14, input signed [15:0] sin_15, output signed [15:0] dout_0, output signed [15:0] dout_1, output signed [15:0] dout_2, output signed [15:0] dout_3, output signed [15:0] dout_4, output signed [15:0] dout_5, output signed [15:0] dout_6, output signed [15:0] dout_7, output signed [15:0] dout_8, output signed [15:0] dout_9, output signed [15:0] dout_10, output signed [15:0] dout_11, output signed [15:0] dout_12, output signed [15:0] dout_13, output signed [15:0] dout_14, output signed [15:0] dout_15 ); reg [3:0]mix_data_vld_dly; wire signed [31:0] mult_icos0_tmp; wire signed [31:0] mult_icos1_tmp; wire signed [31:0] mult_icos2_tmp; wire signed [31:0] mult_icos3_tmp; wire signed [31:0] mult_icos4_tmp; wire signed [31:0] mult_icos5_tmp; wire signed [31:0] mult_icos6_tmp; wire signed [31:0] mult_icos7_tmp; wire signed [31:0] mult_icos8_tmp; wire signed [31:0] mult_icos9_tmp; wire signed [31:0] mult_icos10_tmp; wire signed [31:0] mult_icos11_tmp; wire signed [31:0] mult_icos12_tmp; wire signed [31:0] mult_icos13_tmp; wire signed [31:0] mult_icos14_tmp; wire signed [31:0] mult_icos15_tmp; DW_mult_pipe #(16,16,3,0,1) inst_icos0_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i0),.b(cos_0),.tc(1'b1),.product(mult_icos0_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos1_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i1),.b(cos_1),.tc(1'b1),.product(mult_icos1_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos2_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i2),.b(cos_2),.tc(1'b1),.product(mult_icos2_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos3_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i3),.b(cos_3),.tc(1'b1),.product(mult_icos3_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos4_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i4),.b(cos_4),.tc(1'b1),.product(mult_icos4_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos5_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i5),.b(cos_5),.tc(1'b1),.product(mult_icos5_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos6_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i6),.b(cos_6),.tc(1'b1),.product(mult_icos6_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos7_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i7),.b(cos_7),.tc(1'b1),.product(mult_icos7_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos8_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i8),.b(cos_8),.tc(1'b1),.product(mult_icos8_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos9_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i9),.b(cos_9),.tc(1'b1),.product(mult_icos9_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos10_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i10),.b(cos_10),.tc(1'b1),.product(mult_icos10_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos11_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i11),.b(cos_11),.tc(1'b1),.product(mult_icos11_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos12_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i12),.b(cos_12),.tc(1'b1),.product(mult_icos12_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos13_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i13),.b(cos_13),.tc(1'b1),.product(mult_icos13_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos14_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i14),.b(cos_14),.tc(1'b1),.product(mult_icos14_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_icos15_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_i15),.b(cos_15),.tc(1'b1),.product(mult_icos15_tmp)); wire signed [31:0] mult_qsin0_tmp; wire signed [31:0] mult_qsin1_tmp; wire signed [31:0] mult_qsin2_tmp; wire signed [31:0] mult_qsin3_tmp; wire signed [31:0] mult_qsin4_tmp; wire signed [31:0] mult_qsin5_tmp; wire signed [31:0] mult_qsin6_tmp; wire signed [31:0] mult_qsin7_tmp; wire signed [31:0] mult_qsin8_tmp; wire signed [31:0] mult_qsin9_tmp; wire signed [31:0] mult_qsin10_tmp; wire signed [31:0] mult_qsin11_tmp; wire signed [31:0] mult_qsin12_tmp; wire signed [31:0] mult_qsin13_tmp; wire signed [31:0] mult_qsin14_tmp; wire signed [31:0] mult_qsin15_tmp; DW_mult_pipe #(16,16,3,0,1) inst_qsin0_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q0),.b(sin_0),.tc(1'b1),.product(mult_qsin0_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin1_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q1),.b(sin_1),.tc(1'b1),.product(mult_qsin1_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin2_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q2),.b(sin_2),.tc(1'b1),.product(mult_qsin2_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin3_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q3),.b(sin_3),.tc(1'b1),.product(mult_qsin3_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin4_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q4),.b(sin_4),.tc(1'b1),.product(mult_qsin4_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin5_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q5),.b(sin_5),.tc(1'b1),.product(mult_qsin5_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin6_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q6),.b(sin_6),.tc(1'b1),.product(mult_qsin6_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin7_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q7),.b(sin_7),.tc(1'b1),.product(mult_qsin7_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin8_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q8),.b(sin_8),.tc(1'b1),.product(mult_qsin8_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin9_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q9),.b(sin_9),.tc(1'b1),.product(mult_qsin9_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin10_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q10),.b(sin_10),.tc(1'b1),.product(mult_qsin10_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin11_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q11),.b(sin_11),.tc(1'b1),.product(mult_qsin11_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin12_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q12),.b(sin_12),.tc(1'b1),.product(mult_qsin12_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin13_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q13),.b(sin_13),.tc(1'b1),.product(mult_qsin13_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin14_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q14),.b(sin_14),.tc(1'b1),.product(mult_qsin14_tmp)); DW_mult_pipe #(16,16,3,0,1) inst_qsin15_mult(.clk(clk),.rst_n(rstn),.en(1'b1),.a(din_q15),.b(sin_15),.tc(1'b1),.product(mult_qsin15_tmp)); reg signed [15:0] mult_icos0; reg signed [15:0] mult_icos1; reg signed [15:0] mult_icos2; reg signed [15:0] mult_icos3; reg signed [15:0] mult_icos4; reg signed [15:0] mult_icos5; reg signed [15:0] mult_icos6; reg signed [15:0] mult_icos7; reg signed [15:0] mult_icos8; reg signed [15:0] mult_icos9; reg signed [15:0] mult_icos10; reg signed [15:0] mult_icos11; reg signed [15:0] mult_icos12; reg signed [15:0] mult_icos13; reg signed [15:0] mult_icos14; reg signed [15:0] mult_icos15; wire signed [15:0] mult_icos0_w; wire signed [15:0] mult_icos1_w; wire signed [15:0] mult_icos2_w; wire signed [15:0] mult_icos3_w; wire signed [15:0] mult_icos4_w; wire signed [15:0] mult_icos5_w; wire signed [15:0] mult_icos6_w; wire signed [15:0] mult_icos7_w; wire signed [15:0] mult_icos8_w; wire signed [15:0] mult_icos9_w; wire signed [15:0] mult_icos10_w; wire signed [15:0] mult_icos11_w; wire signed [15:0] mult_icos12_w; wire signed [15:0] mult_icos13_w; wire signed [15:0] mult_icos14_w; wire signed [15:0] mult_icos15_w; assign mult_icos0_w = mult_icos0_tmp[14] ? {mult_icos0_tmp[31] , mult_icos0_tmp[29:15] } + 16'd1 : {mult_icos0_tmp[31] , mult_icos0_tmp[29:15] }; assign mult_icos1_w = mult_icos1_tmp[14] ? {mult_icos1_tmp[31] , mult_icos1_tmp[29:15] } + 16'd1 : {mult_icos1_tmp[31] , mult_icos1_tmp[29:15] }; assign mult_icos2_w = mult_icos2_tmp[14] ? {mult_icos2_tmp[31] , mult_icos2_tmp[29:15] } + 16'd1 : {mult_icos2_tmp[31] , mult_icos2_tmp[29:15] }; assign mult_icos3_w = mult_icos3_tmp[14] ? {mult_icos3_tmp[31] , mult_icos3_tmp[29:15] } + 16'd1 : {mult_icos3_tmp[31] , mult_icos3_tmp[29:15] }; assign mult_icos4_w = mult_icos4_tmp[14] ? {mult_icos4_tmp[31] , mult_icos4_tmp[29:15] } + 16'd1 : {mult_icos4_tmp[31] , mult_icos4_tmp[29:15] }; assign mult_icos5_w = mult_icos5_tmp[14] ? {mult_icos5_tmp[31] , mult_icos5_tmp[29:15] } + 16'd1 : {mult_icos5_tmp[31] , mult_icos5_tmp[29:15] }; assign mult_icos6_w = mult_icos6_tmp[14] ? {mult_icos6_tmp[31] , mult_icos6_tmp[29:15] } + 16'd1 : {mult_icos6_tmp[31] , mult_icos6_tmp[29:15] }; assign mult_icos7_w = mult_icos7_tmp[14] ? {mult_icos7_tmp[31] , mult_icos7_tmp[29:15] } + 16'd1 : {mult_icos7_tmp[31] , mult_icos7_tmp[29:15] }; assign mult_icos8_w = mult_icos8_tmp[14] ? {mult_icos8_tmp[31] , mult_icos8_tmp[29:15] } + 16'd1 : {mult_icos8_tmp[31] , mult_icos8_tmp[29:15] }; assign mult_icos9_w = mult_icos9_tmp[14] ? {mult_icos9_tmp[31] , mult_icos9_tmp[29:15] } + 16'd1 : {mult_icos9_tmp[31] , mult_icos9_tmp[29:15] }; assign mult_icos10_w =mult_icos10_tmp[14]? {mult_icos10_tmp[31], mult_icos10_tmp[29:15]} + 16'd1 : {mult_icos10_tmp[31], mult_icos10_tmp[29:15]}; assign mult_icos11_w =mult_icos11_tmp[14]? {mult_icos11_tmp[31], mult_icos11_tmp[29:15]} + 16'd1 : {mult_icos11_tmp[31], mult_icos11_tmp[29:15]}; assign mult_icos12_w =mult_icos12_tmp[14]? {mult_icos12_tmp[31], mult_icos12_tmp[29:15]} + 16'd1 : {mult_icos12_tmp[31], mult_icos12_tmp[29:15]}; assign mult_icos13_w =mult_icos13_tmp[14]? {mult_icos13_tmp[31], mult_icos13_tmp[29:15]} + 16'd1 : {mult_icos13_tmp[31], mult_icos13_tmp[29:15]}; assign mult_icos14_w =mult_icos14_tmp[14]? {mult_icos14_tmp[31], mult_icos14_tmp[29:15]} + 16'd1 : {mult_icos14_tmp[31], mult_icos14_tmp[29:15]}; assign mult_icos15_w =mult_icos15_tmp[14]? {mult_icos15_tmp[31], mult_icos15_tmp[29:15]} + 16'd1 : {mult_icos15_tmp[31], mult_icos15_tmp[29:15]}; always@(posedge clk)begin if(mix_data_vld_dly[1]) begin mult_icos0 <= mult_icos0_w; mult_icos1 <= mult_icos1_w; mult_icos2 <= mult_icos2_w; mult_icos3 <= mult_icos3_w; mult_icos4 <= mult_icos4_w; mult_icos5 <= mult_icos5_w; mult_icos6 <= mult_icos6_w; mult_icos7 <= mult_icos7_w; mult_icos8 <= mult_icos8_w; mult_icos9 <= mult_icos9_w; mult_icos10 <= mult_icos10_w; mult_icos11 <= mult_icos11_w; mult_icos12 <= mult_icos12_w; mult_icos13 <= mult_icos13_w; mult_icos14 <= mult_icos14_w; mult_icos15 <= mult_icos15_w; end else begin mult_icos0 <= 16'b0; mult_icos1 <= 16'b0; mult_icos2 <= 16'b0; mult_icos3 <= 16'b0; mult_icos4 <= 16'b0; mult_icos5 <= 16'b0; mult_icos6 <= 16'b0; mult_icos7 <= 16'b0; mult_icos8 <= 16'b0; mult_icos9 <= 16'b0; mult_icos10 <= 16'b0; mult_icos11 <= 16'b0; mult_icos12 <= 16'b0; mult_icos13 <= 16'b0; mult_icos14 <= 16'b0; mult_icos15 <= 16'b0; end end reg signed [15:0] mult_qsin0; reg signed [15:0] mult_qsin1; reg signed [15:0] mult_qsin2; reg signed [15:0] mult_qsin3; reg signed [15:0] mult_qsin4; reg signed [15:0] mult_qsin5; reg signed [15:0] mult_qsin6; reg signed [15:0] mult_qsin7; reg signed [15:0] mult_qsin8; reg signed [15:0] mult_qsin9; reg signed [15:0] mult_qsin10; reg signed [15:0] mult_qsin11; reg signed [15:0] mult_qsin12; reg signed [15:0] mult_qsin13; reg signed [15:0] mult_qsin14; reg signed [15:0] mult_qsin15; wire signed [15:0] mult_qsin0_w; wire signed [15:0] mult_qsin1_w; wire signed [15:0] mult_qsin2_w; wire signed [15:0] mult_qsin3_w; wire signed [15:0] mult_qsin4_w; wire signed [15:0] mult_qsin5_w; wire signed [15:0] mult_qsin6_w; wire signed [15:0] mult_qsin7_w; wire signed [15:0] mult_qsin8_w; wire signed [15:0] mult_qsin9_w; wire signed [15:0] mult_qsin10_w; wire signed [15:0] mult_qsin11_w; wire signed [15:0] mult_qsin12_w; wire signed [15:0] mult_qsin13_w; wire signed [15:0] mult_qsin14_w; wire signed [15:0] mult_qsin15_w; assign mult_qsin0_w = mult_qsin0_tmp[14] ? {mult_qsin0_tmp[31] , mult_qsin0_tmp[29:15] } + 16'd1 : {mult_qsin0_tmp[31] , mult_qsin0_tmp[29:15] }; assign mult_qsin1_w = mult_qsin1_tmp[14] ? {mult_qsin1_tmp[31] , mult_qsin1_tmp[29:15] } + 16'd1 : {mult_qsin1_tmp[31] , mult_qsin1_tmp[29:15] }; assign mult_qsin2_w = mult_qsin2_tmp[14] ? {mult_qsin2_tmp[31] , mult_qsin2_tmp[29:15] } + 16'd1 : {mult_qsin2_tmp[31] , mult_qsin2_tmp[29:15] }; assign mult_qsin3_w = mult_qsin3_tmp[14] ? {mult_qsin3_tmp[31] , mult_qsin3_tmp[29:15] } + 16'd1 : {mult_qsin3_tmp[31] , mult_qsin3_tmp[29:15] }; assign mult_qsin4_w = mult_qsin4_tmp[14] ? {mult_qsin4_tmp[31] , mult_qsin4_tmp[29:15] } + 16'd1 : {mult_qsin4_tmp[31] , mult_qsin4_tmp[29:15] }; assign mult_qsin5_w = mult_qsin5_tmp[14] ? {mult_qsin5_tmp[31] , mult_qsin5_tmp[29:15] } + 16'd1 : {mult_qsin5_tmp[31] , mult_qsin5_tmp[29:15] }; assign mult_qsin6_w = mult_qsin6_tmp[14] ? {mult_qsin6_tmp[31] , mult_qsin6_tmp[29:15] } + 16'd1 : {mult_qsin6_tmp[31] , mult_qsin6_tmp[29:15] }; assign mult_qsin7_w = mult_qsin7_tmp[14] ? {mult_qsin7_tmp[31] , mult_qsin7_tmp[29:15] } + 16'd1 : {mult_qsin7_tmp[31] , mult_qsin7_tmp[29:15] }; assign mult_qsin8_w = mult_qsin8_tmp[14] ? {mult_qsin8_tmp[31] , mult_qsin8_tmp[29:15] } + 16'd1 : {mult_qsin8_tmp[31] , mult_qsin8_tmp[29:15] }; assign mult_qsin9_w = mult_qsin9_tmp[14] ? {mult_qsin9_tmp[31] , mult_qsin9_tmp[29:15] } + 16'd1 : {mult_qsin9_tmp[31] , mult_qsin9_tmp[29:15] }; assign mult_qsin10_w = mult_qsin10_tmp[14]? {mult_qsin10_tmp[31], mult_qsin10_tmp[29:15]} + 16'd1 : {mult_qsin10_tmp[31], mult_qsin10_tmp[29:15]}; assign mult_qsin11_w = mult_qsin11_tmp[14]? {mult_qsin11_tmp[31], mult_qsin11_tmp[29:15]} + 16'd1 : {mult_qsin11_tmp[31], mult_qsin11_tmp[29:15]}; assign mult_qsin12_w = mult_qsin12_tmp[14]? {mult_qsin12_tmp[31], mult_qsin12_tmp[29:15]} + 16'd1 : {mult_qsin12_tmp[31], mult_qsin12_tmp[29:15]}; assign mult_qsin13_w = mult_qsin13_tmp[14]? {mult_qsin13_tmp[31], mult_qsin13_tmp[29:15]} + 16'd1 : {mult_qsin13_tmp[31], mult_qsin13_tmp[29:15]}; assign mult_qsin14_w = mult_qsin14_tmp[14]? {mult_qsin14_tmp[31], mult_qsin14_tmp[29:15]} + 16'd1 : {mult_qsin14_tmp[31], mult_qsin14_tmp[29:15]}; assign mult_qsin15_w = mult_qsin15_tmp[14]? {mult_qsin15_tmp[31], mult_qsin15_tmp[29:15]} + 16'd1 : {mult_qsin15_tmp[31], mult_qsin15_tmp[29:15]}; always@(posedge clk)begin if(mix_data_vld_dly[1]) begin mult_qsin0 <= mult_qsin0_w; mult_qsin1 <= mult_qsin1_w; mult_qsin2 <= mult_qsin2_w; mult_qsin3 <= mult_qsin3_w; mult_qsin4 <= mult_qsin4_w; mult_qsin5 <= mult_qsin5_w; mult_qsin6 <= mult_qsin6_w; mult_qsin7 <= mult_qsin7_w; mult_qsin8 <= mult_qsin8_w; mult_qsin9 <= mult_qsin9_w; mult_qsin10 <= mult_qsin10_w; mult_qsin11 <= mult_qsin11_w; mult_qsin12 <= mult_qsin12_w; mult_qsin13 <= mult_qsin13_w; mult_qsin14 <= mult_qsin14_w; mult_qsin15 <= mult_qsin15_w; end else begin mult_qsin0 <= 16'b0; mult_qsin1 <= 16'b0; mult_qsin2 <= 16'b0; mult_qsin3 <= 16'b0; mult_qsin4 <= 16'b0; mult_qsin5 <= 16'b0; mult_qsin6 <= 16'b0; mult_qsin7 <= 16'b0; mult_qsin8 <= 16'b0; mult_qsin9 <= 16'b0; mult_qsin10 <= 16'b0; mult_qsin11 <= 16'b0; mult_qsin12 <= 16'b0; mult_qsin13 <= 16'b0; mult_qsin14 <= 16'b0; mult_qsin15 <= 16'b0; end end wire signed [16:0] ssb0_pt; wire signed [16:0] ssb1_pt; wire signed [16:0] ssb2_pt; wire signed [16:0] ssb3_pt; wire signed [16:0] ssb4_pt; wire signed [16:0] ssb5_pt; wire signed [16:0] ssb6_pt; wire signed [16:0] ssb7_pt; wire signed [16:0] ssb8_pt; wire signed [16:0] ssb9_pt; wire signed [16:0] ssb10_pt; wire signed [16:0] ssb11_pt; wire signed [16:0] ssb12_pt; wire signed [16:0] ssb13_pt; wire signed [16:0] ssb14_pt; wire signed [16:0] ssb15_pt; /* DW01_addsub #(16) inst_dw01_addsub_0(.A(mult_icos0),.B(mult_qsin0),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb0_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_1(.A(mult_icos1),.B(mult_qsin1),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb1_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_2(.A(mult_icos2),.B(mult_qsin2),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb2_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_3(.A(mult_icos3),.B(mult_qsin3),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb3_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_4(.A(mult_icos4),.B(mult_qsin4),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb4_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_5(.A(mult_icos5),.B(mult_qsin5),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb5_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_6(.A(mult_icos6),.B(mult_qsin6),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb6_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_7(.A(mult_icos7),.B(mult_qsin7),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb7_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_8(.A(mult_icos8),.B(mult_qsin8),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb8_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_9(.A(mult_icos9),.B(mult_qsin9),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb9_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_10(.A(mult_icos10),.B(mult_qsin10),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb10_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_11(.A(mult_icos11),.B(mult_qsin11),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb11_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_12(.A(mult_icos12),.B(mult_qsin12),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb12_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_13(.A(mult_icos13),.B(mult_qsin13),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb13_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_14(.A(mult_icos14),.B(mult_qsin14),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb14_pt),.CO()); DW01_addsub #(16) inst_dw01_addsub_15(.A(mult_icos15),.B(mult_qsin15),.CI(1'b0),.ADD_SUB(sel_sideband),.SUM(ssb15_pt),.CO()); */ assign ssb0_pt = sel_sideband ? mult_icos0 - mult_qsin0 : mult_icos0 + mult_qsin0 ; assign ssb1_pt = sel_sideband ? mult_icos1 - mult_qsin1 : mult_icos1 + mult_qsin1 ; assign ssb2_pt = sel_sideband ? mult_icos2 - mult_qsin2 : mult_icos2 + mult_qsin2 ; assign ssb3_pt = sel_sideband ? mult_icos3 - mult_qsin3 : mult_icos3 + mult_qsin3 ; assign ssb4_pt = sel_sideband ? mult_icos4 - mult_qsin4 : mult_icos4 + mult_qsin4 ; assign ssb5_pt = sel_sideband ? mult_icos5 - mult_qsin5 : mult_icos5 + mult_qsin5 ; assign ssb6_pt = sel_sideband ? mult_icos6 - mult_qsin6 : mult_icos6 + mult_qsin6 ; assign ssb7_pt = sel_sideband ? mult_icos7 - mult_qsin7 : mult_icos7 + mult_qsin7 ; assign ssb8_pt = sel_sideband ? mult_icos8 - mult_qsin8 : mult_icos8 + mult_qsin8 ; assign ssb9_pt = sel_sideband ? mult_icos9 - mult_qsin9 : mult_icos9 + mult_qsin9 ; assign ssb10_pt = sel_sideband ? mult_icos10 - mult_qsin10 : mult_icos10 + mult_qsin10; assign ssb11_pt = sel_sideband ? mult_icos11 - mult_qsin11 : mult_icos11 + mult_qsin11; assign ssb12_pt = sel_sideband ? mult_icos12 - mult_qsin12 : mult_icos12 + mult_qsin12; assign ssb13_pt = sel_sideband ? mult_icos13 - mult_qsin13 : mult_icos13 + mult_qsin13; assign ssb14_pt = sel_sideband ? mult_icos14 - mult_qsin14 : mult_icos14 + mult_qsin14; assign ssb15_pt = sel_sideband ? mult_icos15 - mult_qsin15 : mult_icos15 + mult_qsin15; wire signed [15:0] ssb0_w; wire signed [15:0] ssb1_w; wire signed [15:0] ssb2_w; wire signed [15:0] ssb3_w; wire signed [15:0] ssb4_w; wire signed [15:0] ssb5_w; wire signed [15:0] ssb6_w; wire signed [15:0] ssb7_w; wire signed [15:0] ssb8_w; wire signed [15:0] ssb9_w; wire signed [15:0] ssb10_w; wire signed [15:0] ssb11_w; wire signed [15:0] ssb12_w; wire signed [15:0] ssb13_w; wire signed [15:0] ssb14_w; wire signed [15:0] ssb15_w; assign ssb0_w = (ssb0_pt[16:15] == 2'b01) ? 16'd32767 : (ssb0_pt[16:15] == 2'b10) ? -16'd32768 : {ssb0_pt[16],ssb0_pt[14:0]}; assign ssb1_w = (ssb1_pt[16:15] == 2'b01) ? 16'd32767 : (ssb1_pt[16:15] == 2'b10) ? -16'd32768 : {ssb1_pt[16],ssb1_pt[14:0]}; assign ssb2_w = (ssb2_pt[16:15] == 2'b01) ? 16'd32767 : (ssb2_pt[16:15] == 2'b10) ? -16'd32768 : {ssb2_pt[16],ssb2_pt[14:0]}; assign ssb3_w = (ssb3_pt[16:15] == 2'b01) ? 16'd32767 : (ssb3_pt[16:15] == 2'b10) ? -16'd32768 : {ssb3_pt[16],ssb3_pt[14:0]}; assign ssb4_w = (ssb4_pt[16:15] == 2'b01) ? 16'd32767 : (ssb4_pt[16:15] == 2'b10) ? -16'd32768 : {ssb4_pt[16],ssb4_pt[14:0]}; assign ssb5_w = (ssb5_pt[16:15] == 2'b01) ? 16'd32767 : (ssb5_pt[16:15] == 2'b10) ? -16'd32768 : {ssb5_pt[16],ssb5_pt[14:0]}; assign ssb6_w = (ssb6_pt[16:15] == 2'b01) ? 16'd32767 : (ssb6_pt[16:15] == 2'b10) ? -16'd32768 : {ssb6_pt[16],ssb6_pt[14:0]}; assign ssb7_w = (ssb7_pt[16:15] == 2'b01) ? 16'd32767 : (ssb7_pt[16:15] == 2'b10) ? -16'd32768 : {ssb7_pt[16],ssb7_pt[14:0]}; assign ssb8_w = (ssb8_pt[16:15] == 2'b01) ? 16'd32767 : (ssb8_pt[16:15] == 2'b10) ? -16'd32768 : {ssb8_pt[16],ssb8_pt[14:0]}; assign ssb9_w = (ssb9_pt[16:15] == 2'b01) ? 16'd32767 : (ssb9_pt[16:15] == 2'b10) ? -16'd32768 : {ssb9_pt[16],ssb9_pt[14:0]}; assign ssb10_w = (ssb10_pt[16:15] == 2'b01) ? 16'd32767 : (ssb10_pt[16:15] == 2'b10) ? -16'd32768 : {ssb10_pt[16],ssb10_pt[14:0]}; assign ssb11_w = (ssb11_pt[16:15] == 2'b01) ? 16'd32767 : (ssb11_pt[16:15] == 2'b10) ? -16'd32768 : {ssb11_pt[16],ssb11_pt[14:0]}; assign ssb12_w = (ssb12_pt[16:15] == 2'b01) ? 16'd32767 : (ssb12_pt[16:15] == 2'b10) ? -16'd32768 : {ssb12_pt[16],ssb12_pt[14:0]}; assign ssb13_w = (ssb13_pt[16:15] == 2'b01) ? 16'd32767 : (ssb13_pt[16:15] == 2'b10) ? -16'd32768 : {ssb13_pt[16],ssb13_pt[14:0]}; assign ssb14_w = (ssb14_pt[16:15] == 2'b01) ? 16'd32767 : (ssb14_pt[16:15] == 2'b10) ? -16'd32768 : {ssb14_pt[16],ssb14_pt[14:0]}; assign ssb15_w = (ssb15_pt[16:15] == 2'b01) ? 16'd32767 : (ssb15_pt[16:15] == 2'b10) ? -16'd32768 : {ssb15_pt[16],ssb15_pt[14:0]}; reg signed [15:0] ssb0; reg signed [15:0] ssb1; reg signed [15:0] ssb2; reg signed [15:0] ssb3; reg signed [15:0] ssb4; reg signed [15:0] ssb5; reg signed [15:0] ssb6; reg signed [15:0] ssb7; reg signed [15:0] ssb8; reg signed [15:0] ssb9; reg signed [15:0] ssb10; reg signed [15:0] ssb11; reg signed [15:0] ssb12; reg signed [15:0] ssb13; reg signed [15:0] ssb14; reg signed [15:0] ssb15; always@(posedge clk)begin if(mix_data_vld_dly[2]) begin ssb0 <= ssb0_w; ssb1 <= ssb1_w; ssb2 <= ssb2_w; ssb3 <= ssb3_w; ssb4 <= ssb4_w; ssb5 <= ssb5_w; ssb6 <= ssb6_w; ssb7 <= ssb7_w; ssb8 <= ssb8_w; ssb9 <= ssb9_w; ssb10 <= ssb10_w; ssb11 <= ssb11_w; ssb12 <= ssb12_w; ssb13 <= ssb13_w; ssb14 <= ssb14_w; ssb15 <= ssb15_w; end else begin ssb0 <= 16'b0; ssb1 <= 16'b0; ssb2 <= 16'b0; ssb3 <= 16'b0; ssb4 <= 16'b0; ssb5 <= 16'b0; ssb6 <= 16'b0; ssb7 <= 16'b0; ssb8 <= 16'b0; ssb9 <= 16'b0; ssb10 <= 16'b0; ssb11 <= 16'b0; ssb12 <= 16'b0; ssb13 <= 16'b0; ssb14 <= 16'b0; ssb15 <= 16'b0; end end assign dout_0 = ssb0; assign dout_1 = ssb1; assign dout_2 = ssb2; assign dout_3 = ssb3; assign dout_4 = ssb4; assign dout_5 = ssb5; assign dout_6 = ssb6; assign dout_7 = ssb7; assign dout_8 = ssb8; assign dout_9 = ssb9; assign dout_10 = ssb10; assign dout_11 = ssb11; assign dout_12 = ssb12; assign dout_13 = ssb13; assign dout_14 = ssb14; assign dout_15 = ssb15; always @(posedge clk or negedge rstn) begin if(rstn == 1'b0) begin mix_data_vld_dly <= 4'b0; end else begin mix_data_vld_dly <= {mix_data_vld_dly[2:0], mix_enable & din_vld}; end end assign dout_vld = mix_data_vld_dly[3]; endmodule