//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    duc_hb4_shift.v
//  Department            :    
//  Author                :    
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.8         2024-03-26      thfu			output register
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module 	DUC_HB4	 	(
		 	clk,
		 	rstn,
		 	din_0,	
			din_1,	
			din_2,	 
			din_3,	
			din_4,
			din_5,	
			dout
		 	);		
input		clk;
input		rstn;
input	signed [15:0]	din_0;
input	signed [15:0]	din_1;
input	signed [15:0]	din_2;
input	signed [15:0]	din_3;
input	signed [15:0]	din_4;
input	signed [15:0]	din_5;

output	signed [15:0]	dout;

wire	signed [15:0]	din_0;
wire	signed [15:0]	din_2;
wire	signed [15:0]	din_4;
wire	signed [15:0]	din_5;
wire	signed [15:0]	din_6;


parameter	c0 	= 	14'd101;
parameter	c1 	=  -14'd814;
parameter	c2	=	14'd4809;

reg	signed [16:0]	sum_0_5;
reg	signed [16:0]	sum_1_4;
reg	signed [16:0]	sum_2_3;


always@(posedge clk or negedge rstn)
		if(!rstn)	
			begin
				sum_0_5		<=	'h0;	
				sum_1_4		<=	'h0;	
				sum_2_3		<=	'h0;
			end
		else	
			begin
				sum_0_5		<=	{din_0[15],din_0} + {din_5[15],din_5};
				sum_1_4		<=	{din_1[15],din_1} + {din_4[15],din_4};
				sum_2_3		<=	{din_2[15],din_2} + {din_3[15],din_3};
			end

wire	signed	[18:0]	mult_c0_sum0;
wire	signed	[20:0]	mult_c0_sum1;
wire	signed	[23:0]	mult_c0_sum2;
wire	signed	[24:0]	mult_c0_sum3;

assign	mult_c0_sum0 = {sum_0_5,2'b0}; 	
assign	mult_c0_sum1 = {sum_0_5,4'b0}; 	
assign	mult_c0_sum2 = {sum_0_5,7'b0}; 	
assign	mult_c0_sum3 = {sum_0_5,8'b0}; 	

reg	signed		[25:0]	mult_c0_sum;
always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_c0_sum		<=	'h0;
		else	
			mult_c0_sum		<=	{{7{mult_c0_sum0[18]}},mult_c0_sum0} + {{5{mult_c0_sum1[20]}},mult_c0_sum1} + {{2{mult_c0_sum2[23]}},mult_c0_sum2} + {{1{mult_c0_sum3[24]}},mult_c0_sum3};

wire	signed	[19:0]	mult_c1_sum0;
wire	signed	[22:0]	mult_c1_sum1;
wire	signed	[23:0]	mult_c1_sum2;
wire	signed	[26:0]	mult_c1_sum3;
wire	signed	[27:0]	mult_c1_sum4;

assign	mult_c1_sum0 = {sum_1_4,3'b0}; 	
assign	mult_c1_sum1 = {sum_1_4,6'b0}; 	
assign	mult_c1_sum2 = {sum_1_4,7'b0}; 	
assign	mult_c1_sum3 = {sum_1_4,10'b0}; 	
assign	mult_c1_sum4 = {sum_1_4,11'b0}; 

reg	signed		[28:0]	mult_c1_sum;
always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_c1_sum		<=	'h0;
		else	
			mult_c1_sum		<=	-{{9{mult_c1_sum0[19]}},mult_c1_sum0} + {{6{mult_c1_sum1[22]}},mult_c1_sum1} + {{5{mult_c1_sum2[23]}},mult_c1_sum2} + {{2{mult_c1_sum3[26]}},mult_c1_sum3} + {{1{mult_c1_sum4[27]}},mult_c1_sum4};


wire	signed	[18:0]	mult_c2_sum0;
wire	signed	[21:0]	mult_c2_sum1;
wire	signed	[24:0]	mult_c2_sum2;
wire	signed	[25:0]	mult_c2_sum3;
wire	signed	[27:0]	mult_c2_sum4;
wire	signed	[30:0]	mult_c2_sum5;

assign	mult_c2_sum0 = {sum_2_3,2'b0}; 	
assign	mult_c2_sum1 = {sum_2_3,5'b0}; 	
assign	mult_c2_sum2 = {sum_2_3,8'b0}; 	
assign	mult_c2_sum3 = {sum_2_3,9'b0}; 	
assign	mult_c2_sum4 = {sum_2_3,11'b0}; 	
assign	mult_c2_sum5 = {sum_2_3,14'b0}; 

reg	signed		[31:0]	mult_c2_sum;
always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_c2_sum		<=	'h0;
		else	
			mult_c2_sum		<=	{{13{mult_c2_sum0[18]}},mult_c2_sum0} + {{10{mult_c2_sum1[21]}},mult_c2_sum1} + {{7{mult_c2_sum2[24]}},mult_c2_sum2} + {{6{mult_c2_sum3[25]}},mult_c2_sum3} + {{4{mult_c2_sum4[27]}},mult_c2_sum4} + {{1{mult_c2_sum5[30]}},mult_c2_sum5};



reg	 signed	[32:0]	mult_sum;
wire signed [17:0]	dout0_w;
reg	 signed [15:0]	dout0;

always@(posedge clk or negedge rstn)
		if(!rstn)
			mult_sum		<=	'h0;
		else
			mult_sum	<=	{{7{mult_c0_sum[25]}},mult_c0_sum} - {{4{mult_c1_sum[28]}},mult_c1_sum} + {{1{mult_c2_sum[31]}},mult_c2_sum};

assign dout0_w = mult_sum[32:15]+mult_sum[14];

always@(posedge clk or negedge rstn)
	if(!rstn)
		dout0		<=	'h0;
	else if(dout0_w[16:15]==2'b01)
		dout0	<=	16'd32767;	
	else if(dout0_w[16:15]==2'b10)
		dout0	<=	 -16'd32768;
	else
		dout0	<=	dout0_w[15:0];

assign	dout = dout0;
endmodule