//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    duc_hb3_shift.v
//  Department            :    
//  Author                :    
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.8         2024-03-26      thfu			modify delay
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module 	DUC_HB3_TOP_S2		(clkl,
				rstn,
				din0,
				din1,
                din2,
				din3,
				dout_p0,
				dout_p1,
				dout_p2,
				dout_p3,
				dout_p4,
				dout_p5,
				dout_p6,
				dout_p7
				);
input	clkl,rstn;
input	[15:0]	din0;
input	[15:0]	din1;
input	[15:0]	din2;
input	[15:0]	din3;

output	[15:0]	dout_p0;
output	[15:0]	dout_p1;
output	[15:0]	dout_p2;
output	[15:0]	dout_p3;
output	[15:0]	dout_p4;
output	[15:0]	dout_p5;
output	[15:0]	dout_p6;
output	[15:0]	dout_p7;


reg	[15:0]	din_r1;
reg	[15:0]	din_r2;
reg	[15:0]	din_r3;
reg	[15:0]	din_r4;
reg	[15:0]	din_r5;
reg	[15:0]	din_r6;
reg	[15:0]	din_r7;
reg	[15:0]	din_r8;
reg	[15:0]	din_r9;
reg	[15:0]	din_r10;
reg	[15:0]	din_r11;
reg	[15:0]	din_r12;
reg	[15:0]	din_r13;
reg	[15:0]	din_r14;
reg	[15:0]	din_r15;
reg	[15:0]	din_r16;
reg	[15:0]	din_r17;
reg	[15:0]	din_r18;
reg	[15:0]	din_r19;
reg	[15:0]	din_r20;

always@(posedge clkl or negedge rstn)
	if(!rstn)
	begin
		din_r1	<=	'b0;
		din_r2	<=	'b0;
		din_r3	<=	'b0;
		din_r4	<=	'b0;
		din_r5	<=	'b0;
		din_r6	<=	'b0;
		din_r7	<=	'b0;
	end
	else
	begin
		din_r1	<=	din3;
		din_r5	<=	din_r1;
		din_r9	<=	din_r5;
		din_r13	<=	din_r9;
		din_r17	<=	din_r13;


		din_r2	<=	din2;
		din_r6	<=	din_r2;
		din_r10	<=	din_r6;
		din_r14	<=	din_r10;
		din_r18	<=	din_r14;


		din_r3	<=	din1;
		din_r7	<=	din_r3;
		din_r11	<=	din_r7;
		din_r15	<=	din_r11;
		din_r19	<=	din_r15;

		din_r4	<=	din0;
		din_r8	<=	din_r4;
		din_r12	<=	din_r8;
		din_r16	<=	din_r12;
		din_r20	<=	din_r16;

	end




DUC_HB3	 	inst0_duc_hb3(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din3),	
				.din_1		(din2),	
				.din_2		(din1),	 
				.din_3		(din0),	
				.din_4		(din_r1),
				.din_5		(din_r2),
                .din_6		(din_r3),
                .din_7		(din_r4),				
				.dout		(dout_p1)
		 	);


assign		dout_p0 =       din_r17;


DUC_HB3	 	inst1_duc_hb3(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din2),	
				.din_1		(din1),	
				.din_2		(din0),	 
				.din_3		(din_r1),	
				.din_4		(din_r2),
				.din_5		(din_r3),
                .din_6		(din_r4),
                .din_7		(din_r5),				
				.dout		(dout_p3)
		 	);

assign		dout_p2 =       din_r18;	

DUC_HB3	 	inst2_duc_hb3(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din1),	
				.din_1		(din0),	
				.din_2		(din_r1),	 
				.din_3		(din_r2),	
				.din_4		(din_r3),
				.din_5		(din_r4),
                .din_6		(din_r5),
                .din_7		(din_r6),				
				.dout		(dout_p5)
		 	);

assign		dout_p4 =       din_r19;	

DUC_HB3	 	inst3_duc_hb3(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din0),	
				.din_1		(din_r1),	
				.din_2		(din_r2),	 
				.din_3		(din_r3),	
				.din_4		(din_r4),
				.din_5		(din_r5),
                .din_6		(din_r6),
                .din_7		(din_r7),				
				.dout		(dout_p7)
		 	);

assign		dout_p6 =       din_r20;			
endmodule