module 	DUC_HB1_TOP		(clkl,
				rstn,
				din,
				dout_p0,
				dout_p1
				);
input	clkl,rstn;
input	[15:0]	din;

output	[15:0]	dout_p0;
output	[15:0]	dout_p1;


reg  [15:0]	din_r1;
reg  [15:0]	din_r2;
reg  [15:0]	din_r3;
reg  [15:0]	din_r4;
reg  [15:0]	din_r5;
reg  [15:0]	din_r6;
reg  [15:0]	din_r7;
reg  [15:0]	din_r8;
reg  [15:0]	din_r9;
reg  [15:0]	din_r10;
reg  [15:0]	din_r11;
reg  [15:0]	din_r12;
reg  [15:0]	din_r13;
reg  [15:0]	din_r14;
reg  [15:0]	din_r15;
reg  [15:0]	din_r16;
reg  [15:0]	din_r17;
reg  [15:0]	din_r18;
reg  [15:0]	din_r19;
reg  [15:0]	din_r20;
reg  [15:0]	din_r21;
reg  [15:0]	din_r22;
reg  [15:0]	din_r23;
reg  [15:0]	din_r24;
reg  [15:0]	din_r25;
reg  [15:0]	din_r26;
reg  [15:0]	din_r27;
reg  [15:0]	din_r28;
reg  [15:0]	din_r29;
reg  [15:0]	din_r30;
reg  [15:0]	din_r31;
reg  [15:0]	din_r32;
reg  [15:0]	din_r33;
reg  [15:0]	din_r34;
reg  [15:0]	din_r35;

always@(posedge clkl or negedge rstn)
	if(!rstn)
	begin
		din_r1	<=	'b0;
		din_r2	<=	'b0;
		din_r3	<=	'b0;
		din_r4	<=	'b0;
		din_r5	<=	'b0;
		din_r6	<=	'b0;
		din_r7	<=	'b0;
		din_r8	<=	'b0;
		din_r9	<=	'b0;
		din_r10	<=	'b0;
		din_r11	<=	'b0;
		din_r12	<=	'b0;
		din_r13	<=	'b0;
		din_r14	<=	'b0;
		din_r15	<=	'b0;
		din_r16	<=	'b0;
		din_r17	<=	'b0;
		din_r18	<=	'b0;
		din_r19	<=	'b0;
		din_r20	<=	'b0;
		din_r21	<=	'b0;
		din_r22	<=	'b0;
		din_r23	<=	'b0;
		din_r24	<=	'b0;
		din_r25	<=	'b0;
		din_r26	<=	'b0;
		din_r27	<=	'b0;
		din_r28	<=	'b0;
		din_r29	<=	'b0;
		din_r30	<=	'b0;
		din_r31	<=	'b0;
		din_r32	<=	'b0;
		din_r33	<=	'b0;
		din_r34  <=	'b0;
		din_r35  <=	'b0;
	end
	else
	begin
		din_r1	<=	din;
		din_r2	<=	din_r1;
		din_r3	<=	din_r2;
		din_r4	<=	din_r3;
		din_r5	<=	din_r4;
		din_r6	<=	din_r5;
		din_r7	<=	din_r6;
		din_r8	<=	din_r7;
		din_r9	<=	din_r8;
		din_r10	<=	din_r9;
		din_r11	<=	din_r10;
		din_r12	<=	din_r11;
		din_r13	<=	din_r12;
		din_r14	<=	din_r13;
		din_r15	<=	din_r14;
		din_r16	<=	din_r15;
		din_r17	<=	din_r16;
		din_r18	<=	din_r17;
		din_r19	<=	din_r18;
		din_r20	<=	din_r19;
		din_r21	<=	din_r20;
		din_r22	<=	din_r21;
		din_r23	<=	din_r22;
		din_r24	<=	din_r23;
		din_r25	<=	din_r24;
		din_r26	<=	din_r25;
		din_r27	<=	din_r26;
		din_r28	<=	din_r27;
		din_r29	<=	din_r28;
		din_r30	<=	din_r29;
		din_r31	<=	din_r30;
		din_r32	<=	din_r31;
		din_r33	<=	din_r32;
		din_r34  <=	din_r33;
		din_r35  <=	din_r34;
	end




DUC_HB1	 	inst_duc_hb1(
				.clk		(clkl),	
				.rstn		(rstn),	
				.din_0		(din),	
				.din_1		(din_r1),	
				.din_2		(din_r2),	 
				.din_3		(din_r3),	
				.din_4		(din_r4),
				.din_5		(din_r5),
                .din_6		(din_r6),
                .din_7		(din_r7),
                .din_8		(din_r8),
                .din_9		(din_r9),
                .din_10		(din_r10),
                .din_11		(din_r11),	
				.din_12		(din_r12),	
				.din_13		(din_r13),	
				.din_14		(din_r14),	 
				.din_15		(din_r15),	
				.din_16		(din_r16),
				.din_17		(din_r17),
                .din_18		(din_r18),
                .din_19		(din_r19),
                .din_20		(din_r20),
                .din_21		(din_r21),
                .din_22		(din_r22),
                .din_23		(din_r23),	
				.din_24		(din_r24),	
				.din_25		(din_r25),	
				.din_26		(din_r26),	 
				.din_27		(din_r27),	
				.din_28		(din_r28),
				.din_29		(din_r29),
                .din_30		(din_r30),
                .din_31		(din_r31),
                .din_32		(din_r32),
                .din_33		(din_r33),
                .din_34		(din_r34),
                .din_35		(din_r35),					
				.dout		(dout_p1)
		 	);


assign		dout_p0 =       din_r22;

endmodule