module DUC4(
   input         clkl
  ,input         rstn
  ,input  [2 :0] intp_mode   //3'b000:x1;3'b001:x2;3'b010:x4;3'b011:x8;3'b100:x16;
  ,input         dsp_alwayson
  ,input	 data_vldi
  ,input  [15:0] din
  ,output [15:0] dout_p0
  ,output [15:0] dout_p1
  ,output [15:0] dout_p2
  ,output [15:0] dout_p3
  ,output [15:0] dout_p4
  ,output [15:0] dout_p5
  ,output [15:0] dout_p6
  ,output [15:0] dout_p7
  ,output [15:0] dout_p8
  ,output [15:0] dout_p9
  ,output [15:0] dout_pa
  ,output [15:0] dout_pb
  ,output [15:0] dout_pc
  ,output [15:0] dout_pd
  ,output [15:0] dout_pe
  ,output [15:0] dout_pf
  ,output	 data_vldo
);

wire [15:0] dt1_p_0;
wire [15:0] dt1_p_1;

wire [15:0] dt2_p_0;
wire [15:0] dt2_p_1;
wire [15:0] dt2_p_2;
wire [15:0] dt2_p_3;

wire [15:0] dt3_p_0;
wire [15:0] dt3_p_1;
wire [15:0] dt3_p_2;
wire [15:0] dt3_p_3;
wire [15:0] dt3_p_4;
wire [15:0] dt3_p_5;
wire [15:0] dt3_p_6;
wire [15:0] dt3_p_7;

wire [15:0] dt4_p_0;
wire [15:0] dt4_p_1;
wire [15:0] dt4_p_2;
wire [15:0] dt4_p_3;
wire [15:0] dt4_p_4;
wire [15:0] dt4_p_5;
wire [15:0] dt4_p_6;
wire [15:0] dt4_p_7;
wire [15:0] dt4_p_8;
wire [15:0] dt4_p_9;
wire [15:0] dt4_p_a;
wire [15:0] dt4_p_b;
wire [15:0] dt4_p_c;
wire [15:0] dt4_p_d;
wire [15:0] dt4_p_e;
wire [15:0] dt4_p_f;

reg [15:0] mux_p_0;
reg [15:0] mux_p_1;
reg [15:0] mux_p_2;
reg [15:0] mux_p_3;
reg [15:0] mux_p_4;
reg [15:0] mux_p_5;
reg [15:0] mux_p_6;
reg [15:0] mux_p_7;
reg [15:0] mux_p_8;
reg [15:0] mux_p_9;
reg [15:0] mux_p_a;
reg [15:0] mux_p_b;
reg [15:0] mux_p_c;
reg [15:0] mux_p_d;
reg [15:0] mux_p_e;
reg [15:0] mux_p_f;

reg 	[70:0]	DUC4_data_vld_r;

always@(posedge clkl or negedge rstn)
	if(!rstn)
		begin
			DUC4_data_vld_r	<=	9'b0;			
		end
	else
		begin
			DUC4_data_vld_r	<=	{DUC4_data_vld_r[70:0], data_vldi};
		end

///////////////////////////////////////////////////////
//DUC_HB1_TOP inst
///////////////////////////////////////////////////////
DUC_HB1_TOP U0_DUC_HB1_TOP (
   .clkl    ( clkl    )
  ,.rstn    ( rstn    )
  ,.din     ( din     )
  ,.dout_p0 ( dt1_p_0 )
  ,.dout_p1 ( dt1_p_1 )
  );


///////////////////////////////////////////////////////
//DUC_HB2_TOP_S inst1
///////////////////////////////////////////////////////

DUC_HB2_TOP_S U1_DUC_HB2_TOP (
   .clkl    ( clkl    )
  ,.rstn    ( rstn    )
  ,.din0    ( dt1_p_1 )
  ,.din1    ( dt1_p_0 )
  ,.dout_p0 ( dt2_p_0 )
  ,.dout_p1 ( dt2_p_1 )
  ,.dout_p2 ( dt2_p_2 )
  ,.dout_p3 ( dt2_p_3 )
  );

///////////////////////////////////////////////////////
//DUC_HB3_TOP_S2 inst1
///////////////////////////////////////////////////////

DUC_HB3_TOP_S2 U1_DUC_HB3_TOP (
   .clkl    ( clkl    )
  ,.rstn    ( rstn    )
  ,.din0    ( dt2_p_2 )
  ,.din1    ( dt2_p_3 )
  ,.din2    ( dt2_p_0 )
  ,.din3    ( dt2_p_1 )
  ,.dout_p0 ( dt3_p_0 )
  ,.dout_p1 ( dt3_p_1 )
  ,.dout_p2 ( dt3_p_2 )
  ,.dout_p3 ( dt3_p_3 )
  ,.dout_p4 ( dt3_p_4 )
  ,.dout_p5 ( dt3_p_5 )
  ,.dout_p6 ( dt3_p_6 )
  ,.dout_p7 ( dt3_p_7 )
  ); 

///////////////////////////////////////////////////////
//DUC_HB4_TOP_S3 inst1
///////////////////////////////////////////////////////

DUC_HB4_TOP_S3 U1_DUC_HB4_TOP (
   .clkl    ( clkl    )
  ,.rstn    ( rstn    )
  ,.din0    ( dt3_p_6 )
  ,.din1    ( dt3_p_7 )
  ,.din2    ( dt3_p_4 )
  ,.din3    ( dt3_p_5 )
  ,.din4    ( dt3_p_2 )
  ,.din5    ( dt3_p_3 )
  ,.din6    ( dt3_p_0 )
  ,.din7    ( dt3_p_1 )
  ,.dout_p0 ( dt4_p_0 )
  ,.dout_p1 ( dt4_p_1 )
  ,.dout_p2 ( dt4_p_2 )
  ,.dout_p3 ( dt4_p_3 )
  ,.dout_p4 ( dt4_p_4 )
  ,.dout_p5 ( dt4_p_5 )
  ,.dout_p6 ( dt4_p_6 )
  ,.dout_p7 ( dt4_p_7 )
  ,.dout_p8 ( dt4_p_8 )
  ,.dout_p9 ( dt4_p_9 )
  ,.dout_pa ( dt4_p_a )
  ,.dout_pb ( dt4_p_b )
  ,.dout_pc ( dt4_p_c )
  ,.dout_pd ( dt4_p_d )
  ,.dout_pe ( dt4_p_e )
  ,.dout_pf ( dt4_p_f )
  ); 

always@(posedge clkl) begin
  case(intp_mode)
    3'b000  : begin
	          	  mux_p_0   <= din;
			  mux_p_1   <= 16'h0;
			  mux_p_2   <= 16'h0;
			  mux_p_3   <= 16'h0;
			  mux_p_4   <= 16'h0;
			  mux_p_5   <= 16'h0;
			  mux_p_6   <= 16'h0;
			  mux_p_7   <= 16'h0;
			  mux_p_8   <= 16'h0;
			  mux_p_9   <= 16'h0;
			  mux_p_a   <= 16'h0;
			  mux_p_b   <= 16'h0;
			  mux_p_c   <= 16'h0;
			  mux_p_d   <= 16'h0;
			  mux_p_e   <= 16'h0;
			  mux_p_f   <= 16'h0; 
	end
    3'b001  : begin
	          	  mux_p_0   <= dt1_p_0;
			  mux_p_1   <= 16'h0;
			  mux_p_2   <= 16'h0;
			  mux_p_3   <= 16'h0;
			  mux_p_4   <= 16'h0;
			  mux_p_5   <= 16'h0;
			  mux_p_6   <= 16'h0;
			  mux_p_7   <= 16'h0;
			  mux_p_8   <= dt1_p_1;
			  mux_p_9   <= 16'h0;
			  mux_p_a   <= 16'h0;
			  mux_p_b   <= 16'h0;
			  mux_p_c   <= 16'h0;
			  mux_p_d   <= 16'h0;
			  mux_p_e   <= 16'h0;
			  mux_p_f   <= 16'h0; 
	end
    3'b010  : begin
	          	  mux_p_0   <= dt2_p_1;
			  mux_p_1   <= 16'h0;
			  mux_p_2   <= 16'h0;
			  mux_p_3   <= 16'h0;
			  mux_p_4   <= dt2_p_0;
			  mux_p_5   <= 16'h0;
			  mux_p_6   <= 16'h0;
			  mux_p_7   <= 16'h0;
			  mux_p_8   <= dt2_p_3;
			  mux_p_9   <= 16'h0;
			  mux_p_a   <= 16'h0;
			  mux_p_b   <= 16'h0;
			  mux_p_c   <= dt2_p_2;
			  mux_p_d   <= 16'h0;
			  mux_p_e   <= 16'h0;
			  mux_p_f 	<= 16'h0; 
	end
    3'b011  : begin
	         	  mux_p_0   <= dt3_p_1;
			  mux_p_1   <= 16'h0;
			  mux_p_2   <= dt3_p_0;
			  mux_p_3   <= 16'h0;
			  mux_p_4   <= dt3_p_3;
			  mux_p_5   <= 16'h0;
			  mux_p_6   <= dt3_p_2;
			  mux_p_7   <= 16'h0;
			  mux_p_8   <= dt3_p_5;
			  mux_p_9   <= 16'h0;
			  mux_p_a   <= dt3_p_4;
			  mux_p_b   <= 16'h0;
			  mux_p_c   <= dt3_p_7;
			  mux_p_d   <= 16'h0;
			  mux_p_e   <= dt3_p_6;
			  mux_p_f   <= 16'h0; 
	end
    3'b100  : begin
	         	  mux_p_0   <= dt4_p_1;
			  mux_p_1   <= dt4_p_0;
			  mux_p_2   <= dt4_p_3;
			  mux_p_3   <= dt4_p_2;
			  mux_p_4   <= dt4_p_5;
			  mux_p_5   <= dt4_p_4;
			  mux_p_6   <= dt4_p_7;
			  mux_p_7   <= dt4_p_6;
			  mux_p_8   <= dt4_p_9;
			  mux_p_9   <= dt4_p_8;
			  mux_p_a   <= dt4_p_b;
			  mux_p_b   <= dt4_p_a;
			  mux_p_c   <= dt4_p_d;
			  mux_p_d   <= dt4_p_c;
			  mux_p_e   <= dt4_p_f;
			  mux_p_f   <= dt4_p_e; 
	end
	default : begin
	                  mux_p_0   <= 16'h0;
			  mux_p_1   <= 16'h0;
			  mux_p_2   <= 16'h0;
			  mux_p_3   <= 16'h0;
			  mux_p_4   <= 16'h0;
			  mux_p_5   <= 16'h0;
			  mux_p_6   <= 16'h0;
			  mux_p_7   <= 16'h0;
			  mux_p_8   <= 16'h0;
			  mux_p_9   <= 16'h0;
			  mux_p_a   <= 16'h0;
			  mux_p_b   <= 16'h0;
			  mux_p_c   <= 16'h0;
			  mux_p_d   <= 16'h0;
			  mux_p_e   <= 16'h0;
			  mux_p_f   <= 16'h0; 
	end
  endcase
end  

assign dout_p0 = mux_p_f ;
assign dout_p1 = mux_p_e ;
assign dout_p2 = mux_p_d ;
assign dout_p3 = mux_p_c ;
assign dout_p4 = mux_p_b ;
assign dout_p5 = mux_p_a ;
assign dout_p6 = mux_p_9 ;
assign dout_p7 = mux_p_8 ;
assign dout_p8 = mux_p_7 ;
assign dout_p9 = mux_p_6 ;
assign dout_pa = mux_p_5 ;
assign dout_pb = mux_p_4 ;
assign dout_pc = mux_p_3 ;
assign dout_pd = mux_p_2 ;
assign dout_pe = mux_p_1 ;
assign dout_pf = mux_p_0 ;

reg 	data_vldo_t;

always@(posedge clkl) begin
  if(dsp_alwayson) begin
    data_vldo_t <= 1'b1;
  end
  else begin
    case(intp_mode)
        3'b000  :   data_vldo_t <= data_vldi;
        3'b001  :   data_vldo_t <= DUC4_data_vld_r[21];
        3'b010  :   data_vldo_t <= DUC4_data_vld_r[28];
        3'b011  :   data_vldo_t <= DUC4_data_vld_r[33];
        3'b100  :   data_vldo_t <= DUC4_data_vld_r[37];
        default :	data_vldo_t <= data_vldi;
    endcase
  end
end

assign data_vldo = data_vldo_t;

endmodule