//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : XY_dsp.v // Department : // Author : PWY // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.4 2024-03-12 PWY //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module xy_dsp ( input clk ,input rstn ,input phase_manual_clr ,input phase_auto_clr ,input [47:0] fcw ,input [15:0] pha ,input [1 :0] qam_mod //2'b00:bypass;2'b01:mix; //2'b10:cos;2'b11:sin; ,input sel_sideband //1'b0:Upper sideband;1'b1:Lower sideband; ,input [2 :0] intp_mode //3'b000:x1;3'b001:x2;3'b010:x4; //3'b011:x8;3'b100:x16; ,input [1 :0] dac_mode_sel //2'b00:NRZ mode;2'b01:MIX mode; //2'b10:2xNRZ mode;2'b00:reserve; ,input mix_enable ,input dsp_alwayson ,input [15:0] din_i ,input [15:0] din_q ,input din_vld //data output ,output [15:0] dout0 ,output [15:0] dout1 ,output [15:0] dout2 ,output [15:0] dout3 ,output [15:0] dout4 ,output [15:0] dout5 ,output [15:0] dout6 ,output [15:0] dout7 ,output [15:0] dout8 ,output [15:0] dout9 ,output [15:0] dout10 ,output [15:0] dout11 ,output [15:0] dout12 ,output [15:0] dout13 ,output [15:0] dout14 ,output [15:0] dout15 ,output dout_vld ); wire [15:0] dt_i_0; wire [15:0] dt_i_1; wire [15:0] dt_i_2; wire [15:0] dt_i_3; wire [15:0] dt_i_4; wire [15:0] dt_i_5; wire [15:0] dt_i_6; wire [15:0] dt_i_7; wire [15:0] dt_i_8; wire [15:0] dt_i_9; wire [15:0] dt_i_a; wire [15:0] dt_i_b; wire [15:0] dt_i_c; wire [15:0] dt_i_d; wire [15:0] dt_i_e; wire [15:0] dt_i_f; wire [15:0] dt_q_0; wire [15:0] dt_q_1; wire [15:0] dt_q_2; wire [15:0] dt_q_3; wire [15:0] dt_q_4; wire [15:0] dt_q_5; wire [15:0] dt_q_6; wire [15:0] dt_q_7; wire [15:0] dt_q_8; wire [15:0] dt_q_9; wire [15:0] dt_q_a; wire [15:0] dt_q_b; wire [15:0] dt_q_c; wire [15:0] dt_q_d; wire [15:0] dt_q_e; wire [15:0] dt_q_f; //DUC valid signal wire dout_vld_duc_i; wire dout_vld_duc_q; //mix valid signal wire dout_vld_mix; DUC4 inst_duc_top_i ( .clkl ( clk ) ,.rstn ( rstn ) ,.intp_mode ( intp_mode ) ,.dsp_alwayson ( dsp_alwayson ) ,.din ( din_i ) ,.data_vldi ( din_vld ) ,.data_vldo ( dout_vld_duc_i ) ,.dout_p0 ( dt_i_0 ) ,.dout_p1 ( dt_i_1 ) ,.dout_p2 ( dt_i_2 ) ,.dout_p3 ( dt_i_3 ) ,.dout_p4 ( dt_i_4 ) ,.dout_p5 ( dt_i_5 ) ,.dout_p6 ( dt_i_6 ) ,.dout_p7 ( dt_i_7 ) ,.dout_p8 ( dt_i_8 ) ,.dout_p9 ( dt_i_9 ) ,.dout_pa ( dt_i_a ) ,.dout_pb ( dt_i_b ) ,.dout_pc ( dt_i_c ) ,.dout_pd ( dt_i_d ) ,.dout_pe ( dt_i_e ) ,.dout_pf ( dt_i_f ) ); DUC4 inst_duc_top_q ( .clkl ( clk ) ,.rstn ( rstn ) ,.intp_mode ( intp_mode ) ,.dsp_alwayson ( dsp_alwayson ) ,.din ( din_q ) ,.data_vldi ( din_vld ) ,.data_vldo ( dout_vld_duc_q ) ,.dout_p0 ( dt_q_0 ) ,.dout_p1 ( dt_q_1 ) ,.dout_p2 ( dt_q_2 ) ,.dout_p3 ( dt_q_3 ) ,.dout_p4 ( dt_q_4 ) ,.dout_p5 ( dt_q_5 ) ,.dout_p6 ( dt_q_6 ) ,.dout_p7 ( dt_q_7 ) ,.dout_p8 ( dt_q_8 ) ,.dout_p9 ( dt_q_9 ) ,.dout_pa ( dt_q_a ) ,.dout_pb ( dt_q_b ) ,.dout_pc ( dt_q_c ) ,.dout_pd ( dt_q_d ) ,.dout_pe ( dt_q_e ) ,.dout_pf ( dt_q_f ) ); wire [15:0] qam_0; wire [15:0] qam_1; wire [15:0] qam_2; wire [15:0] qam_3; wire [15:0] qam_4; wire [15:0] qam_5; wire [15:0] qam_6; wire [15:0] qam_7; wire [15:0] qam_8; wire [15:0] qam_9; wire [15:0] qam_a; wire [15:0] qam_b; wire [15:0] qam_c; wire [15:0] qam_d; wire [15:0] qam_e; wire [15:0] qam_f; QAM_TOP inst_qam_top ( .clk ( clk ) ,.rstn ( rstn ) ,.phase_manual_clr ( phase_manual_clr ) ,.phase_auto_clr ( phase_auto_clr ) ,.fcw ( fcw ) ,.pha ( pha ) ,.qam_mod ( qam_mod ) ,.sel_sideband ( sel_sideband ) ,.mix_enable ( mix_enable ) ,.din_vld ( dout_vld_duc_i & dout_vld_duc_q ) ,.dout_vld ( dout_vld_mix ) ,.din_i_0 ( dt_i_0 ) ,.din_i_1 ( dt_i_1 ) ,.din_i_2 ( dt_i_2 ) ,.din_i_3 ( dt_i_3 ) ,.din_i_4 ( dt_i_4 ) ,.din_i_5 ( dt_i_5 ) ,.din_i_6 ( dt_i_6 ) ,.din_i_7 ( dt_i_7 ) ,.din_i_8 ( dt_i_8 ) ,.din_i_9 ( dt_i_9 ) ,.din_i_10 ( dt_i_a ) ,.din_i_11 ( dt_i_b ) ,.din_i_12 ( dt_i_c ) ,.din_i_13 ( dt_i_d ) ,.din_i_14 ( dt_i_e ) ,.din_i_15 ( dt_i_f ) ,.din_q_0 ( dt_q_0 ) ,.din_q_1 ( dt_q_1 ) ,.din_q_2 ( dt_q_2 ) ,.din_q_3 ( dt_q_3 ) ,.din_q_4 ( dt_q_4 ) ,.din_q_5 ( dt_q_5 ) ,.din_q_6 ( dt_q_6 ) ,.din_q_7 ( dt_q_7 ) ,.din_q_8 ( dt_q_8 ) ,.din_q_9 ( dt_q_9 ) ,.din_q_10 ( dt_q_a ) ,.din_q_11 ( dt_q_b ) ,.din_q_12 ( dt_q_c ) ,.din_q_13 ( dt_q_d ) ,.din_q_14 ( dt_q_e ) ,.din_q_15 ( dt_q_f ) ,.dout_i_0 ( qam_0 ) ,.dout_i_1 ( qam_1 ) ,.dout_i_2 ( qam_2 ) ,.dout_i_3 ( qam_3 ) ,.dout_i_4 ( qam_4 ) ,.dout_i_5 ( qam_5 ) ,.dout_i_6 ( qam_6 ) ,.dout_i_7 ( qam_7 ) ,.dout_i_8 ( qam_8 ) ,.dout_i_9 ( qam_9 ) ,.dout_i_10 ( qam_a ) ,.dout_i_11 ( qam_b ) ,.dout_i_12 ( qam_c ) ,.dout_i_13 ( qam_d ) ,.dout_i_14 ( qam_e ) ,.dout_i_15 ( qam_f ) ); dacif dacif_inst ( .clk ( clk ) ,.rstn ( rstn ) ,.dac_mode_sel ( dac_mode_sel ) ,.intp_mode ( intp_mode ) ,.din_vld ( dout_vld_mix ) ,.dout_vld ( dout_vld ) ,.din0 ( qam_0 ) ,.din1 ( qam_1 ) ,.din2 ( qam_2 ) ,.din3 ( qam_3 ) ,.din4 ( qam_4 ) ,.din5 ( qam_5 ) ,.din6 ( qam_6 ) ,.din7 ( qam_7 ) ,.din8 ( qam_8 ) ,.din9 ( qam_9 ) ,.din10 ( qam_a ) ,.din11 ( qam_b ) ,.din12 ( qam_c ) ,.din13 ( qam_d ) ,.din14 ( qam_e ) ,.din15 ( qam_f ) ,.dout0 ( dout0 ) ,.dout1 ( dout1 ) ,.dout2 ( dout2 ) ,.dout3 ( dout3 ) ,.dout4 ( dout4 ) ,.dout5 ( dout5 ) ,.dout6 ( dout6 ) ,.dout7 ( dout7 ) ,.dout8 ( dout8 ) ,.dout9 ( dout9 ) ,.dout10 ( dout10 ) ,.dout11 ( dout11 ) ,.dout12 ( dout12 ) ,.dout13 ( dout13 ) ,.dout14 ( dout14 ) ,.dout15 ( dout15 ) ); endmodule